Chinh L Nguyen

US Patent:

6473827, Oct 29, 2002

Filed:

Dec 22, 1998

Appl. No.:

09/218954

Inventors:

Robert James McMillen - Carlsbad CA
Chinh Kim Nguyen - San Diego CA

Assignee:

NCR Corporation - Dayton OH

International Classification:

G06F 1300

US Classification:

710316

Abstract:

An interconnect network having a plurality of identical fabrics partitions the switching elements of the fabrics, so that many links can be combined into single cables. In the partitioning method, one or more of the switching elements from the first stage of each of the fabrics are physically packaged onto the same board called a concentrator, and these concentrators are physically distributed among the processing nodes connected to the interconnect network. The concentrator allows all the links from each processing node to a concentrator, each of which need to be connected to different fabrics, to be combined into a single cable. Furthermore, the concentrator allows all the links from a single switching element in the first stage to be combined into a single cable to be connected to the subsequent or expansion (second and higher) stages of the fabric. The subsequent or expansion stages of each fabric can be implemented independently of other fabrics in a centralized location.

US Patent:

6795886, Sep 21, 2004

Filed:

Dec 22, 2000

Appl. No.:

09/746915

Inventors:

Chinh K. Nguyen - San Diego CA

Assignee:

NCR Corporation - Dayton OH

International Classification:

G06F 1300

US Classification:

710310, 710316, 370412

Abstract:

An interconnect switch is used to couple input ports and output ports. The interconnect switch includes a central buffer having a number of storage entries to store data units from input ports. When an output port is available, data unit(s) are transferred from the central buffer to an output port. A main pointer queue contains addresses that point to storage entries in the central buffer.

US Patent:

20030110335, Jun 12, 2003

Filed:

Jun 12, 2000

Appl. No.:

09/593033

Inventors:

CHINH NGUYEN - SAN DIEGO CA, US

Assignee:

NCR CORPORATION - DAYTON 45479

International Classification:

G06F013/00
G06F013/38

US Classification:

710/107000

Abstract:

A method and apparatus of performing transactions over a bus includes sending, from a first device, an indication to start a bus transaction. Assertion of a predetermined indication from a second device is waited for. An indication that the first device is ready to transfer data over the bus is asserted after assertion of the predetermined indication. In one arrangement, the bus is a Peripheral Component Interconnect (PCI) bus.

US Patent:

57128510, Jan 27, 1998

Filed:

Dec 28, 1995

Appl. No.:

8/579961

Inventors:

Chinh Kim Nguyen - San Diego CA
Sunder Raj Rathnavelu - Marlboro NJ
Don Tipon - San Diego CA

Assignee:

Lucent Technologies Inc. - Murray Hill NJ

International Classification:

H04L 1256

US Classification:

370399

Abstract:

An apparatus an method for adaptive time slot scheduling of communications traffic generated by end-point host in ATM network. The scheduler includes a time slot ring including an array of time slots, wherein each of said time slots includes a virtual channel identifier (VCID) of a virtual channel (VC) to be serviced; a VC table including an array of VC descriptors, wherein the VCID stored in said time slot ring points to a VC descriptor in the VC table; and processor for scheduling the VCs in said time slots of said time slot ring, wherein the time slots ring are circularly processed in a continuous fashion thereby enabling scheduled transmission of ATM cells in the network. The processor is operable to queue the VCID of a newly calculated target slot in an already occupied time slot if the newly calculated target slot is occupied, thereby creating a linked list of VCs, and the processor is operable to service all VCs at a single time slot before proceeding to a next time slot.

US Patent:

47978171, Jan 10, 1989

Filed:

Dec 10, 1986

Appl. No.:

6/940315

Inventors:

Chinh K. Nguyen - San Diego CA
Charles A. Flicek - Escondido CA

Assignee:

NCR Corporation - Dayton OH

International Classification:

G06F 900
G06F 930
G06F 938
G06F 906

US Classification:

364200

Abstract:

A device is described by this disclosure for performing memory stores in a memory of a computer system. The computer system includes a processor having a pipeline for processing commands in multiple stages; wherein the commands include a plurality of instructions, including store instructions, and virtual addresses. When the processor processes a store command, the pipeline is blocked until the associated virtual address is translated by a translation device to a real address. In the present device, if a selected store operation is processed, a check is made to see if the associated virtual address has previously been translated, and if it has, the pipeline is unblocked, thus enhancing the processing of store operations.

US Patent:

60523875, Apr 18, 2000

Filed:

Oct 31, 1997

Appl. No.:

8/961873

Inventors:

Kit Man Chow - Carlsbad CA
Chinh Kim Nguyen - San Diego CA

Assignee:

NCR Corporation - Dayton OH

International Classification:

H04L 1200

US Classification:

370474

Abstract:

An enhanced interface between a processor and an Asynchronous Transfer Mode (ATM) segmentation controller. A software driver communicates with the controller to efficiently segment protocol data units (PDUs) into ATM cells for transmission. The software driver creates a series of data structures in memory for managing the PDU, wherein the data structures include a linked list of buffer descriptors that describe the size and location of subportions of the PDU. The ATM controller is capable of accessing and interpreting these data structures. As a result, only a single I/O operation is required for the software driver to initiate direct memory access (DMA) operations by the ATM controller to retrieve the data structures from memory and subsequently transmit the PDU.

US Patent:

58599622, Jan 12, 1999

Filed:

Dec 21, 1995

Appl. No.:

8/576655

Inventors:

Donald G. Tipon - San Diego CA
Steven J. Schlesinger - Escondido CA
Chinh Kim Nguyen - San Diego CA
Darrin J. Marshall - San Diego CA

Assignee:

NCR Corporation - Dayton OH

International Classification:

G06F 1100

US Classification:

39518309

Abstract:

A system for verifying design of a digital system. A digital system, which receives input vectors and produces output vectors, is simulated. The invention generates a sequence of synthesized input vectors, and applies them to the simulated system. These input vectors cause changes in internal variables, and the output vectors. The invention also independently computes the values which internal variables and output vectors are expected to assume. The invention then compares the simulated internal and output variables with the computed values. If they agree, the simulation is assumed to function properly.