Chinh Phu Nguyen

US Patent:

8581348, Nov 12, 2013

Filed:

Dec 13, 2011

Appl. No.:

13/324699

Inventors:

Mahbub Rashed - Santa Clara CA, US
Steven Soss - Cornwall NY, US
Jongwook Kye - Pleasanton CA, US
Irene Y. Lin - Los Altos Hills CA, US
James Benjamin Gullette - Wadesboro NC, US
Chinh Nguyen - Austin TX, US
Jeff Kim - San Jose CA, US
Marc Tarabbia - Pleasant Valley NY, US
Yuansheng Ma - Santa Clara CA, US
Yunfei Deng - Sunnyvale CA, US
Rod Augur - Hopewell Junction NY, US
Seung-Hyun Rhee - Fishkill NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Danbury CT, US

Assignee:

GLOBALFOUNDRIES, Inc. - Grand Cayman

International Classification:

H01L 27/088
H01L 21/70
H01L 21/02

US Classification:

257401, 257368, 257369, 257382, 257384

Abstract:

A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors includes a source, a drain, and a gate. A CA layer is electrically connected to at least one of the source or the drain of the first transistor. A CB layer is electrically connected to at least one of the gates of the transistors and the CA layer.

US Patent:

8618607, Dec 31, 2013

Filed:

Jul 2, 2012

Appl. No.:

13/539830

Inventors:

Mahbub Rashed - Santa Clara CA, US
David Doman - Austin TX, US
Marc Tarabbia - Pleasant Valley NY, US
Irene Lin - Los Altos Hills CA, US
Jeff Kim - San Jose CA, US
Chinh Nguyen - Austin TX, US
Steve Soss - Cornwall NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Malta NY, US

Assignee:

GLOBALFOUNDRIES Inc. - Grand Cayman

International Classification:

H01L 21/02

US Classification:

257359, 257369, 257379, 257E21602, 257E21656, 257E23144, 257E23152, 257E27029, 257E27081, 257E29226, 257E29276

Abstract:

One illustrative device disclosed herein includes a continuous active region defined in a semiconducting substrate, first and second transistors formed in and above the continuous active region, each of the first and second transistors comprising a plurality of doped regions formed in the continuous active region, a conductive isolating electrode positioned above the continuous active region between the first and second transistors and a power rail conductively coupled to the conductive isolating electrode.

US Patent:

20130146986, Jun 13, 2013

Filed:

Dec 13, 2011

Appl. No.:

13/324740

Inventors:

Mahbub Rashed - Santa Clara CA, US
Irene Y. Lin - Los Altos Hills CA, US
Steven Soss - Cornwall NY, US
Jeff Kim - San Jose CA, US
Chinh Nguyen - Austin TX, US
Marc Tarabbia - Pleasant Valley NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Danbury CT, US

International Classification:

H01L 27/092
H01L 27/088

US Classification:

257369, 257368, 257E27062, 257E2706

Abstract:

A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.

US Patent:

20140027918, Jan 30, 2014

Filed:

Jul 30, 2012

Appl. No.:

13/561932

Inventors:

Mahbub Rashed - Santa Clara CA, US
Marc Tarabbia - Pleasant Valley NY, US
Chinh Nguyen - Austin TX, US
David Doman - Austin TX, US
Juhan Kim - Santa Clara CA, US
Xiang Qi - San Jose CA, US
Suresh Venkatesan - Danbury CT, US

Assignee:

GLOBALFOUNDRIES Inc. - Grand Cayman

International Classification:

H01L 23/535
H01L 21/768

US Classification:

257773, 438599, 257E2159, 257E23168

Abstract:

An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a first gate cut region across the first gate structure, and a second gate cut region across the second gate structure; providing a first gate contact over the first gate structure, and a second gate contact over the second gate structure; and providing a diffusion contact structure between the first and second gate cut regions to couple the first gate contact to the second gate contact.

US Patent:

59093927, Jun 1, 1999

Filed:

Oct 9, 1997

Appl. No.:

8/948531

Inventors:

Chinh D. Nguyen - San Jose CA
Guy S. Yuen - San Jose CA
Chi-Tay Huang - Fremont CA

Assignee:

Programmable Microelectronics Corporation - San Jose CA

International Classification:

G11C 1604

US Classification:

36518512

Abstract:

A nonvolatile PMOS memory array includes a plurality of pages, where each column of a page includes two series-connected PMOS OR strings in parallel with a bit line. Each PMOS OR string includes a PMOS select transistor coupled between the bit line and two series connected PMOS floating gate memory cells. The PMOS floating gate memory cells are programmed via channel hot electron (CHE) injection and erased via electron tunneling. A soft-program mechanism is used to compensate for over-erasing of the memory cells. In some embodiments, the bit lines are segmented along page boundaries to increase speed.

US Patent:

59739673, Oct 26, 1999

Filed:

Dec 5, 1997

Appl. No.:

8/985561

Inventors:

Chinh D. Nguyen - San Jose CA
Andy Teng-Feng Yu - Palo Alto CA
Vikram Kowshik - San Jose CA
Vishal Sarin - Santa Clara CA

Assignee:

Programmable Microelectronics Corporation - San Jose CA

International Classification:

G11C 1604
G11C 1100

US Classification:

36518905

Abstract:

A page buffer facilitates programming of a memory cell within an associated memory array by selectively connecting a bit line associated with the memory cell to a negative voltage supply in response to the logic state of a data signal. The page buffer includes an SRAM latch having first and second nodes, a cross-coupled latch having first and second nodes, and a pass transistor. The first node of the SRAM latch is coupled to receive the data signal and to a first control terminal of the cross-coupled latch. The second node of the SRAM latch is coupled to a second control terminal of the cross-coupled latch. The second node of the cross-coupled latch is coupled to a gate of the pass transistor which, in turn, is connected between the bit line and the negative voltage supply. When the data signal is in a first logic state, the cross-coupled latch turns on the pass transistor and, in connecting the bit line to the negative voltage supply, facilitates programming of the cell. When the data signal is in a second logic state, the cross-coupled latch turns off the pass transistor and allows the bit line to float which, in turn, precludes programming of the cell.

US Patent:

62047213, Mar 20, 2001

Filed:

May 20, 1998

Appl. No.:

9/082485

Inventors:

Guy S. Yuen - San Jose CA
Chinh D. Nguyen - San Jose CA

Assignee:

Programmable Microelectronics Corp. - San Jose CA

International Classification:

H03K 031

US Classification:

327534

Abstract:

A switching circuit includes a switch having first and second terminals coupled between a voltage supply and ground potential and having a control terminal coupled to receive a control signal indicative of the output voltage of an associated semiconductor circuit. The switch also includes an output terminal coupled to the well region within which is formed the associated semiconductor circuit. In preferred embodiments, the control signal transitions from a first state to a second state when the output voltage exceeds a predetermined potential. In response thereto, the switching circuit changes the well potential of the associated semiconductor circuit from a first voltage to ground potential, wherein the first voltage is greater than ground potential.

US Patent:

58019944, Sep 1, 1998

Filed:

Aug 15, 1997

Appl. No.:

8/911968

Inventors:

Chinh D. Nguyen - San Jose CA
Guy S. Yuen - San Jose CA

Assignee:

Programmable Microelectronics Corporation - San Jose CA

International Classification:

G11C 1604

US Classification:

36518529

Abstract:

A memory array includes a predetermined number of rows of PMOS Flash memory cells formed in each of a plurality of n- well regions of a semiconductor substrate, where each of the n- well regions defines a page of the memory array. In some embodiments, a plurality of bit lines define columns of the memory array, where the p+ drain of each of the memory cells in a common column are coupled to an associated one of the bit lines. In other embodiments, a plurality of sub-bit lines define columns of the memory array, where the p+ drain of each of the memory cells in a common column are coupled to an associated one of the sub-bit lines, and groups of a predetermined number of the sub-bit lines are selectively coupled to associated ones of a plurality of bit lines via pass transistors. During erasing operations a selected n- well region, within which are formed the memory cells of a selected page, is held at a first voltage, while the other n- well regions, within which are formed the memory cells of the respective un-selected pages, are held at a second voltage. The first and second voltages are different, thereby isolating the un-selected pages from erasing operations of the selected page.