Chinh V Nguyen

US Patent:

57676542, Jun 16, 1998

Filed:

Nov 26, 1996

Appl. No.:

8/756058

Inventors:

Paolo Menegoli - Milpitas CA
Chinh Nguyen - Sunnyvale CA

Assignee:

SGS-Thomson Microelectronics, Inc. - Carrollton TX

International Classification:

H02P 528

US Classification:

318811

Abstract:

A pulse width modulated (PWM) motor drive with back EMF monitoring of the floating phase of a polyphase motor is arranged so that zero crossings of the back EMF can be read without interference by PWM switching. A measure is taken of an interval between two zero crossings and, in the next interval, the PWM switching is stopped near to and before the next expected zero crossing, based on the time of the last prior interval. A period counter counts up during the first interval and another counter, loaded with the previous count reached by the period counter, counts down at the same rate during the second interval until a certain number is reached, near to but before zero, to generate a signal that results in stopping PWM switching until after the next zero crossing is detected.

US Patent:

20220367360, Nov 17, 2022

Filed:

Aug 2, 2022

Appl. No.:

17/879574

Inventors:

- Malta NY, US
Irene Y. Lin - Los Altos Hills CA, US
Steven Soss - Cornwall NY, US
Jeff Kim - San Jose CA, US
Chinh Nguyen - Austin TX, US
Marc Tarabbia - Pleasant Valley NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Danbury CT, US

International Classification:

H01L 23/535
H01L 21/8234
H01L 27/02
H01L 21/768
H01L 21/285
H01L 21/8238
H01L 23/532
H01L 27/092
H01L 29/08

Abstract:

A semiconductor device including four transistors. Gates of first and third transistors extend longitudinally as part of a first linear strip. Gates of second and fourth transistors extend longitudinally as part of a second linear strip parallel to and spaced apart from first linear strip. Aligned first and second gate cut isolations separate gates of first and second transistor from gates of third transistor and fourth transistor respectively. First and second CB layers connect to the gate of first transistor and second transistor respectively. CA layer extends longitudinally between first end and second end of CA layer connects to CB layers. CB layers are electrically connected to gates of first transistor adjacent first end of CA layer and second transistor adjacent second end of CA layer respectively. CA layer extends substantially parallel to first and second linear strips and is substantially perpendicular to first and second CB layers.

US Patent:

20210013150, Jan 14, 2021

Filed:

Sep 30, 2020

Appl. No.:

17/039187

Inventors:

- Grand Cayman, KY
Irene Y. Lin - Los Altos Hills CA, US
Steven Soss - Cornwall NY, US
Jeff Kim - San Jose CA, US
Chinh Nguyen - Austin TX, US
Marc Tarabbia - Pleasant Valley NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Danbury CT, US

International Classification:

H01L 23/535
H01L 21/8234
H01L 27/02
H01L 21/768
H01L 21/285
H01L 21/8238
H01L 23/532
H01L 27/092
H01L 29/08

Abstract:

A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate. The first transistor and a second transistor are formed on the semiconductor substrate. Each transistor comprises a source, a drain, and a gate. The gate of the first transistor extends longitudinally as part of a first linear strip and the gate of the second transistor extends longitudinally as part of the second linear strip parallel to and spaced apart from the first linear strip. A first CB layer forms a local interconnect layer electrically connected to the gate of the first transistor. A second CB layer forms a local interconnect layer electrically connected to the gate of the second transistor. A CA layer forms a local interconnect layer extending longitudinally between a first end and a second end of the CA layer. The CA layer is electrically connected to the first and second CB layers. The first CB layer is electrically connected adjacent the first end of the CA layer and the second layer is electrically connected adjacent the second end of the CA layer. The first CB layer, the second CB layer and the CA layer are disposed between a first metal layer and the semiconductor substrate. The first metal layer being disposed above each source, each drain, and each gate of the first and second transistors. The CA layer extends substantially parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers. At least one via selectively provides an electrical connection between the CA or CB layers and the at least one metal layer.

US Patent:

20160268204, Sep 15, 2016

Filed:

May 25, 2016

Appl. No.:

15/164114

Inventors:

- Grand Cayman, KY
Irene Y. Lin - Los Altos Hills CA, US
Steven Soss - Cornwall NY, US
Jeff Kim - San Jose CA, US
Chinh Nguyen - Austin TX, US
Marc Tarabbia - Pleasant Valley NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Danbury CT, US

International Classification:

H01L 23/535
H01L 29/08
H01L 27/092
H01L 23/532
H01L 21/8238
H01L 21/285

Abstract:

A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.