Chinh Trung Nguyen

US Patent:

6473827, Oct 29, 2002

Filed:

Dec 22, 1998

Appl. No.:

09/218954

Inventors:

Robert James McMillen - Carlsbad CA
Chinh Kim Nguyen - San Diego CA

Assignee:

NCR Corporation - Dayton OH

International Classification:

G06F 1300

US Classification:

710316

Abstract:

An interconnect network having a plurality of identical fabrics partitions the switching elements of the fabrics, so that many links can be combined into single cables. In the partitioning method, one or more of the switching elements from the first stage of each of the fabrics are physically packaged onto the same board called a concentrator, and these concentrators are physically distributed among the processing nodes connected to the interconnect network. The concentrator allows all the links from each processing node to a concentrator, each of which need to be connected to different fabrics, to be combined into a single cable. Furthermore, the concentrator allows all the links from a single switching element in the first stage to be combined into a single cable to be connected to the subsequent or expansion (second and higher) stages of the fabric. The subsequent or expansion stages of each fabric can be implemented independently of other fabrics in a centralized location.

US Patent:

6795886, Sep 21, 2004

Filed:

Dec 22, 2000

Appl. No.:

09/746915

Inventors:

Chinh K. Nguyen - San Diego CA

Assignee:

NCR Corporation - Dayton OH

International Classification:

G06F 1300

US Classification:

710310, 710316, 370412

Abstract:

An interconnect switch is used to couple input ports and output ports. The interconnect switch includes a central buffer having a number of storage entries to store data units from input ports. When an output port is available, data unit(s) are transferred from the central buffer to an output port. A main pointer queue contains addresses that point to storage entries in the central buffer.

US Patent:

8581348, Nov 12, 2013

Filed:

Dec 13, 2011

Appl. No.:

13/324699

Inventors:

Mahbub Rashed - Santa Clara CA, US
Steven Soss - Cornwall NY, US
Jongwook Kye - Pleasanton CA, US
Irene Y. Lin - Los Altos Hills CA, US
James Benjamin Gullette - Wadesboro NC, US
Chinh Nguyen - Austin TX, US
Jeff Kim - San Jose CA, US
Marc Tarabbia - Pleasant Valley NY, US
Yuansheng Ma - Santa Clara CA, US
Yunfei Deng - Sunnyvale CA, US
Rod Augur - Hopewell Junction NY, US
Seung-Hyun Rhee - Fishkill NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Danbury CT, US

Assignee:

GLOBALFOUNDRIES, Inc. - Grand Cayman

International Classification:

H01L 27/088
H01L 21/70
H01L 21/02

US Classification:

257401, 257368, 257369, 257382, 257384

Abstract:

A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors includes a source, a drain, and a gate. A CA layer is electrically connected to at least one of the source or the drain of the first transistor. A CB layer is electrically connected to at least one of the gates of the transistors and the CA layer.

US Patent:

8618607, Dec 31, 2013

Filed:

Jul 2, 2012

Appl. No.:

13/539830

Inventors:

Mahbub Rashed - Santa Clara CA, US
David Doman - Austin TX, US
Marc Tarabbia - Pleasant Valley NY, US
Irene Lin - Los Altos Hills CA, US
Jeff Kim - San Jose CA, US
Chinh Nguyen - Austin TX, US
Steve Soss - Cornwall NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Malta NY, US

Assignee:

GLOBALFOUNDRIES Inc. - Grand Cayman

International Classification:

H01L 21/02

US Classification:

257359, 257369, 257379, 257E21602, 257E21656, 257E23144, 257E23152, 257E27029, 257E27081, 257E29226, 257E29276

Abstract:

One illustrative device disclosed herein includes a continuous active region defined in a semiconducting substrate, first and second transistors formed in and above the continuous active region, each of the first and second transistors comprising a plurality of doped regions formed in the continuous active region, a conductive isolating electrode positioned above the continuous active region between the first and second transistors and a power rail conductively coupled to the conductive isolating electrode.

US Patent:

20030110335, Jun 12, 2003

Filed:

Jun 12, 2000

Appl. No.:

09/593033

Inventors:

CHINH NGUYEN - SAN DIEGO CA, US

Assignee:

NCR CORPORATION - DAYTON 45479

International Classification:

G06F013/00
G06F013/38

US Classification:

710/107000

Abstract:

A method and apparatus of performing transactions over a bus includes sending, from a first device, an indication to start a bus transaction. Assertion of a predetermined indication from a second device is waited for. An indication that the first device is ready to transfer data over the bus is asserted after assertion of the predetermined indication. In one arrangement, the bus is a Peripheral Component Interconnect (PCI) bus.

US Patent:

20130146986, Jun 13, 2013

Filed:

Dec 13, 2011

Appl. No.:

13/324740

Inventors:

Mahbub Rashed - Santa Clara CA, US
Irene Y. Lin - Los Altos Hills CA, US
Steven Soss - Cornwall NY, US
Jeff Kim - San Jose CA, US
Chinh Nguyen - Austin TX, US
Marc Tarabbia - Pleasant Valley NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Danbury CT, US

International Classification:

H01L 27/092
H01L 27/088

US Classification:

257369, 257368, 257E27062, 257E2706

Abstract:

A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.

US Patent:

20140027918, Jan 30, 2014

Filed:

Jul 30, 2012

Appl. No.:

13/561932

Inventors:

Mahbub Rashed - Santa Clara CA, US
Marc Tarabbia - Pleasant Valley NY, US
Chinh Nguyen - Austin TX, US
David Doman - Austin TX, US
Juhan Kim - Santa Clara CA, US
Xiang Qi - San Jose CA, US
Suresh Venkatesan - Danbury CT, US

Assignee:

GLOBALFOUNDRIES Inc. - Grand Cayman

International Classification:

H01L 23/535
H01L 21/768

US Classification:

257773, 438599, 257E2159, 257E23168

Abstract:

An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a first gate cut region across the first gate structure, and a second gate cut region across the second gate structure; providing a first gate contact over the first gate structure, and a second gate contact over the second gate structure; and providing a diffusion contact structure between the first and second gate cut regions to couple the first gate contact to the second gate contact.

US Patent:

59093927, Jun 1, 1999

Filed:

Oct 9, 1997

Appl. No.:

8/948531

Inventors:

Chinh D. Nguyen - San Jose CA
Guy S. Yuen - San Jose CA
Chi-Tay Huang - Fremont CA

Assignee:

Programmable Microelectronics Corporation - San Jose CA

International Classification:

G11C 1604

US Classification:

36518512

Abstract:

A nonvolatile PMOS memory array includes a plurality of pages, where each column of a page includes two series-connected PMOS OR strings in parallel with a bit line. Each PMOS OR string includes a PMOS select transistor coupled between the bit line and two series connected PMOS floating gate memory cells. The PMOS floating gate memory cells are programmed via channel hot electron (CHE) injection and erased via electron tunneling. A soft-program mechanism is used to compensate for over-erasing of the memory cells. In some embodiments, the bit lines are segmented along page boundaries to increase speed.