Chinh Tung Nguyen

US Patent:

6566610, May 20, 2003

Filed:

Nov 1, 2001

Appl. No.:

10/032908

Inventors:

Chinh Nguyen - Irvine CA
Phu Hoang - Foothill Ranch CA
Phan Hoang - Mission Viejo CA
Andy Le - Garden Grove CA

Assignee:

Virtium Technology, Inc. - Irvine CA

International Classification:

H05K 116

US Classification:

174260, 29840, 29842

Abstract:

In one embodiment of the invention, a stacking element includes a printed circuit board (PCB) and a plurality of solder bumps. The PCB has a top side and a bottom side. The top side is attached to first pins of a first device. The plurality of solder bumps are on the bottom side and attached to upper areas of second pins of a second device to provide electrical connections between the first pins and the second pins.

US Patent:

7167373, Jan 23, 2007

Filed:

Mar 8, 2004

Appl. No.:

10/796540

Inventors:

Phan Hoang - Mission Viejo CA, US
Chinh Nguyen - Irvine CA, US
Frank Hoang - Foothill Ranch CA, US
Andy Le - Garden Grove CA, US

Assignee:

Virtium Technology, Inc. - Rancho Santa Margarita CA

International Classification:

H05K 7/06

US Classification:

361749, 361803, 174254, 257686, 29840, 438109

Abstract:

One embodiment of the invention includes a flexible circuit and a stiffener. The flexible circuit has first, second, and third portions. The first portion is folded on an upper surface of the third portion and has first contact elements attached to a first device. The second portion is folded on the first device and has second contact elements attached to a second device. The stiffener is attached to the upper surface of the third portion and located between the upper surface of the third portion and the first portion.

US Patent:

7786563, Aug 31, 2010

Filed:

Jun 28, 2007

Appl. No.:

11/824168

Inventors:

Phan Hoang - Placentia CA, US
Chinh Nguyen - Irvine CA, US
Anthony Tran - Fountain Valley CA, US
Tung Dang - Tustin CA, US

Assignee:

Virtium Technology, Inc. - Rancho Santa Margarita CA

International Classification:

H01L 23/02

US Classification:

257686, 257783, 257734, 257E23036, 257E21524

Abstract:

An embodiment of the present invention is a technique to stack multiple devices using an interconnecting element. A board has a periphery and top and bottom surfaces. The top surface has top contact pads to attach to a first device. The bottom surface is milled down to form a cavity confined by vertical walls around the periphery. The cavity fits a second device. Bottom contact pads are formed on bottom side of the vertical walls. The bottom contact pads are raised with respect to the bottom side of the vertical walls. Traces internal to the board connect the bottom contact pads to the top contact pads.

US Patent:

8124450, Feb 28, 2012

Filed:

Jul 27, 2010

Appl. No.:

12/844795

Inventors:

Phan Hoang - Placentia CA, US
Chinh Nguyen - Irvine CA, US
Anthony Tran - Fountain Valley CA, US
Tung Dang - Tustin CA, US

Assignee:

Virtium Technology, Inc. - Rancho Santa Margarita CA

International Classification:

H01L 21/00

US Classification:

438107, 257E21499

Abstract:

An embodiment of the present invention is a technique to stack multiple devices using an interconnecting element. A board has a periphery and top and bottom surfaces. The top surface has top contact pads to attach to a first device. The bottom surface is milled down to form a cavity confined by vertical walls around the periphery. The cavity fits a second device. Bottom contact pads are formed on bottom side of the vertical walls. The bottom contact pads are raised with respect to the bottom side of the vertical walls. Traces internal to the board connect the bottom contact pads to the top contact pads.

US Patent:

20030164247, Sep 4, 2003

Filed:

Apr 1, 2003

Appl. No.:

10/404266

Inventors:

Chinh Nguyen - Irvine CA, US
Phu Hoang - Foothill Ranch CA, US
Phan Hoang - Mission Viejo CA, US
Andy Le - Garden Grove CA, US

International Classification:

H05K001/16

US Classification:

174/260000

Abstract:

In one embodiment of the invention, a stacking element includes a printed circuit board (PCB) and a plurality of solder bumps. The PCB has a top side and a bottom side. The top side is attached to first pins of a first device. The plurality of solder bumps are on the bottom side and attached to upper areas of second pins of a second device to provide electrical connections between the first pins and the second pins.

US Patent:

20110074002, Mar 31, 2011

Filed:

Sep 30, 2009

Appl. No.:

12/571313

Inventors:

Phan Hoang - Rancho Santa Margarita CA, US
Chinh Minh Nguyen - Irvine CA, US

Assignee:

VIRTIUM TECHNOLOGY, INC. - Rancho Santa Margarita CA

International Classification:

H01L 25/11
H01L 21/50

US Classification:

257686, 438107, 257E21499, 257E25027

Abstract:

An embodiment is a method and apparatus to stack devices. A first finished package level (FPL) device having a first grounded tested die (GTD) is reduced to nearly size of the first GTD. The first FPL has a first plurality of solder balls. The reduced first FPL device is attached to a first substrate to form a first device assembly.