Chinh L Nguyen

US Patent:

8581348, Nov 12, 2013

Filed:

Dec 13, 2011

Appl. No.:

13/324699

Inventors:

Mahbub Rashed - Santa Clara CA, US
Steven Soss - Cornwall NY, US
Jongwook Kye - Pleasanton CA, US
Irene Y. Lin - Los Altos Hills CA, US
James Benjamin Gullette - Wadesboro NC, US
Chinh Nguyen - Austin TX, US
Jeff Kim - San Jose CA, US
Marc Tarabbia - Pleasant Valley NY, US
Yuansheng Ma - Santa Clara CA, US
Yunfei Deng - Sunnyvale CA, US
Rod Augur - Hopewell Junction NY, US
Seung-Hyun Rhee - Fishkill NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Danbury CT, US

Assignee:

GLOBALFOUNDRIES, Inc. - Grand Cayman

International Classification:

H01L 27/088
H01L 21/70
H01L 21/02

US Classification:

257401, 257368, 257369, 257382, 257384

Abstract:

A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors includes a source, a drain, and a gate. A CA layer is electrically connected to at least one of the source or the drain of the first transistor. A CB layer is electrically connected to at least one of the gates of the transistors and the CA layer.

US Patent:

8598633, Dec 3, 2013

Filed:

Jan 16, 2012

Appl. No.:

13/351101

Inventors:

Marc Tarabbia - Pleasant Valley NY, US
James B. Gullette - Dresden, DE
Mahbub Rashed - Santa Clara CA, US
David S. Doman - Austin TX, US
Irene Y. Lin - Los Altos Hills CA, US
Ingolf Lorenz - Ottendorf-Okrilla, DE
Larry Ho - Cupertino CA, US
Chinh Nguyen - Austin TX, US
Jeff Kim - San Jose CA, US
Jongwook Kye - Pleasanton CA, US
Yuansheng Ma - Santa Clara CA, US
Yunfei Deng - Sunnyvale CA, US
Rod Augur - Hopewell Junction NY, US
Seung-Hyun Rhee - Fishkill NY, US
Jason E. Stephens - Beacon NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Danbury CT, US

Assignee:

GLOBALFOUNDRIES, Inc. - Grand Cayman

International Classification:

H01L 23/52

US Classification:

257207, 257211

Abstract:

A semiconductor device includes a semiconductor substrate having a diffusion region. A transistor is formed within the diffusion region. A power rail is disposed outside the diffusion region. A contact layer is disposed above the substrate and below the power rail. A via is disposed between the contact layer and the power rail to electrically connect the contact layer to the power rail. The contact layer includes a first length disposed outside the diffusion region and a second length extending from the first length into the diffusion region and electrically connected to the transistor.

US Patent:

8618607, Dec 31, 2013

Filed:

Jul 2, 2012

Appl. No.:

13/539830

Inventors:

Mahbub Rashed - Santa Clara CA, US
David Doman - Austin TX, US
Marc Tarabbia - Pleasant Valley NY, US
Irene Lin - Los Altos Hills CA, US
Jeff Kim - San Jose CA, US
Chinh Nguyen - Austin TX, US
Steve Soss - Cornwall NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Malta NY, US

Assignee:

GLOBALFOUNDRIES Inc. - Grand Cayman

International Classification:

H01L 21/02

US Classification:

257359, 257369, 257379, 257E21602, 257E21656, 257E23144, 257E23152, 257E27029, 257E27081, 257E29226, 257E29276

Abstract:

One illustrative device disclosed herein includes a continuous active region defined in a semiconducting substrate, first and second transistors formed in and above the continuous active region, each of the first and second transistors comprising a plurality of doped regions formed in the continuous active region, a conductive isolating electrode positioned above the continuous active region between the first and second transistors and a power rail conductively coupled to the conductive isolating electrode.

US Patent:

20130146986, Jun 13, 2013

Filed:

Dec 13, 2011

Appl. No.:

13/324740

Inventors:

Mahbub Rashed - Santa Clara CA, US
Irene Y. Lin - Los Altos Hills CA, US
Steven Soss - Cornwall NY, US
Jeff Kim - San Jose CA, US
Chinh Nguyen - Austin TX, US
Marc Tarabbia - Pleasant Valley NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Danbury CT, US

International Classification:

H01L 27/092
H01L 27/088

US Classification:

257369, 257368, 257E27062, 257E2706

Abstract:

A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate with a first transistor and a second transistor formed on the semiconductor substrate. Each of the transistors comprises a source, a drain, and a gate. A trench silicide layer electrically connects one of the source or the drain of the first transistor to one of the source or the drain of the second transistor.

US Patent:

20140027918, Jan 30, 2014

Filed:

Jul 30, 2012

Appl. No.:

13/561932

Inventors:

Mahbub Rashed - Santa Clara CA, US
Marc Tarabbia - Pleasant Valley NY, US
Chinh Nguyen - Austin TX, US
David Doman - Austin TX, US
Juhan Kim - Santa Clara CA, US
Xiang Qi - San Jose CA, US
Suresh Venkatesan - Danbury CT, US

Assignee:

GLOBALFOUNDRIES Inc. - Grand Cayman

International Classification:

H01L 23/535
H01L 21/768

US Classification:

257773, 438599, 257E2159, 257E23168

Abstract:

An approach for providing cross-coupling-based designs using diffusion contact structures is disclosed. Embodiments include providing first and second gate structures over a substrate; providing a first gate cut region across the first gate structure, and a second gate cut region across the second gate structure; providing a first gate contact over the first gate structure, and a second gate contact over the second gate structure; and providing a diffusion contact structure between the first and second gate cut regions to couple the first gate contact to the second gate contact.

US Patent:

20220367360, Nov 17, 2022

Filed:

Aug 2, 2022

Appl. No.:

17/879574

Inventors:

- Malta NY, US
Irene Y. Lin - Los Altos Hills CA, US
Steven Soss - Cornwall NY, US
Jeff Kim - San Jose CA, US
Chinh Nguyen - Austin TX, US
Marc Tarabbia - Pleasant Valley NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Danbury CT, US

International Classification:

H01L 23/535
H01L 21/8234
H01L 27/02
H01L 21/768
H01L 21/285
H01L 21/8238
H01L 23/532
H01L 27/092
H01L 29/08

Abstract:

A semiconductor device including four transistors. Gates of first and third transistors extend longitudinally as part of a first linear strip. Gates of second and fourth transistors extend longitudinally as part of a second linear strip parallel to and spaced apart from first linear strip. Aligned first and second gate cut isolations separate gates of first and second transistor from gates of third transistor and fourth transistor respectively. First and second CB layers connect to the gate of first transistor and second transistor respectively. CA layer extends longitudinally between first end and second end of CA layer connects to CB layers. CB layers are electrically connected to gates of first transistor adjacent first end of CA layer and second transistor adjacent second end of CA layer respectively. CA layer extends substantially parallel to first and second linear strips and is substantially perpendicular to first and second CB layers.

US Patent:

20210013150, Jan 14, 2021

Filed:

Sep 30, 2020

Appl. No.:

17/039187

Inventors:

- Grand Cayman, KY
Irene Y. Lin - Los Altos Hills CA, US
Steven Soss - Cornwall NY, US
Jeff Kim - San Jose CA, US
Chinh Nguyen - Austin TX, US
Marc Tarabbia - Pleasant Valley NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Danbury CT, US

International Classification:

H01L 23/535
H01L 21/8234
H01L 27/02
H01L 21/768
H01L 21/285
H01L 21/8238
H01L 23/532
H01L 27/092
H01L 29/08

Abstract:

A semiconductor device is provided for implementing at least one logic element. The semiconductor device includes a semiconductor substrate. The first transistor and a second transistor are formed on the semiconductor substrate. Each transistor comprises a source, a drain, and a gate. The gate of the first transistor extends longitudinally as part of a first linear strip and the gate of the second transistor extends longitudinally as part of the second linear strip parallel to and spaced apart from the first linear strip. A first CB layer forms a local interconnect layer electrically connected to the gate of the first transistor. A second CB layer forms a local interconnect layer electrically connected to the gate of the second transistor. A CA layer forms a local interconnect layer extending longitudinally between a first end and a second end of the CA layer. The CA layer is electrically connected to the first and second CB layers. The first CB layer is electrically connected adjacent the first end of the CA layer and the second layer is electrically connected adjacent the second end of the CA layer. The first CB layer, the second CB layer and the CA layer are disposed between a first metal layer and the semiconductor substrate. The first metal layer being disposed above each source, each drain, and each gate of the first and second transistors. The CA layer extends substantially parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers. At least one via selectively provides an electrical connection between the CA or CB layers and the at least one metal layer.

US Patent:

20190326219, Oct 24, 2019

Filed:

Jul 3, 2019

Appl. No.:

16/502521

Inventors:

Mahbub Rashed - Santa Clara CA, US
Irene Y. Lin - Los Altos Hills CA, US
Steven Soss - Cornwall NY, US
Jeff Kim - San Jose CA, US
Chinh Nguyen - Austin TX, US
Marc Tarabbia - Pleasant Valley NY, US
Scott Johnson - Wappingers Falls NY, US
Subramani Kengeri - San Jose CA, US
Suresh Venkatesan - Danbury CT, US

International Classification:

H01L 23/535
H01L 29/08
H01L 27/092
H01L 23/532
H01L 21/8238
H01L 21/8234
H01L 21/285
H01L 27/02
H01L 21/768

Abstract:

A semiconductor device includes a substrate with first and second transistors disposed thereon and including sources, drains, and gates, wherein the first and second gates extend longitudinally as part of linear strips that are parallel to and spaced apart. The device further includes a first CB layer forming a local interconnect electrically connected to the first gate, a second CB layer forming a local interconnect electrically connected to the second gate, and a CA layer forming a local interconnect extending longitudinally between first and second ends of the CA layer. The first and second CB layers and the CA layer are disposed between a first metal layer and the substrate. The first metal layer is disposed above each source, drain, and gate of the transistors, The CA layer extends parallel to the first and second linear strips and is substantially perpendicular to the first and second CB layers.