Chinh Trung Tran

US Patent:

59745428, Oct 26, 1999

Filed:

Oct 30, 1997

Appl. No.:

8/960818

Inventors:

Chinh N. Tran - Austin TX
W. Kurt Lewchuk - Austin TX

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G06F 940

US Classification:

712239

Abstract:

A branch prediction unit includes a cache-line based branch prediction storage having a branch prediction storage location assigned to each cache line of an instruction cache within the microprocessor employing the branch prediction unit. Although each branch prediction storage location is assigned to a particular cache line, the branch prediction storage location stores an alternate target indication indicating whether a branch prediction within the storage location corresponds to a branch instruction within the cache line to which the storage location is assigned or to a branch instruction within a different cache line. The different cache line has a predetermined relationship to the cache line to which the storage location is assigned. In various embodiments, the different cache line is at an index one less than the index of the storage location or is within a different way of the same index. The branch prediction unit described herein approximates having multiple branch predictions per cache line even though only one branch prediction storage location is assigned to the cache line.

US Patent:

55198376, May 21, 1996

Filed:

Jul 29, 1994

Appl. No.:

8/282332

Inventors:

Chinh N. Tran - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 13364
G06F 1300

US Classification:

395291

Abstract:

Systems and methods for arbitrating access to shared resources in a computer system, the systems and methods providing fairness, high throughput, timely response and area efficient implementation. In one form, the pseudo-round-robin arbitration system is composed of a binary tree architecture of round-robin cells. The requests are combined in various groupings and simultaneously provided to all the cells in the multiple levels of the hierarchy. The grant signals are generated from the lowest level of cells. The hierarchy defines that the outputs of the higher level cells serve as enablements to successively related lower level cells in progression by level. A preferred cell for the binary version of the pseudo-round-robin tree architecture is composed of two OR type gates and two AND type gates, the latter gates receiving the enablement signal from the cell in the next higher level of the tree.