Chinna Babu Prudvi

US Patent:

6378048, Apr 23, 2002

Filed:

Nov 12, 1998

Appl. No.:

09/190126

Inventors:

Chinna Prudvi - Portland OR
Paul Breuder - Beaverton OR
Quinn W. Merrill - Phoenix AZ
Derek Bachand - Portland OR
Harish kumar Kumar - Portland OR
Brent E. Lince - Hillsboro OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1300

US Classification:

711144, 711122, 711146

Abstract:

A cache coherency method, a data eviction method, and a multi-level cache system are disclosed. A copy of data may take one of five states including a shared state, a lazy state, an invalid state, a modified state, and an exclusive state. Based upon the names of these states, the disclosed methods and systems may be labeled âSLIME. â The method of cache coherency may include storing a copy of data in a cache and storing state information identifying the copy as being stored in one of the five above-mentioned states. In response to a snoop request related to the data, marking a status field indicative of the state of the data to represent that the data is shared without regard to the datas dirty status. The data eviction method includes storing data in a cache, storing a status field in association with the data, the status field having a first sub-field to indicate whether the data is dirty and a second sub-field to indicate whether the data is shared, when the data is to be evicted from the cache, testing the first sub-field field to determine whether the data is dirty and, if so, writing the data to another cache before evicting the data from the cache. The multi-layer cache system includes first and second caches provided in a layered arrangement with the second cache being in a higher layer than the first cache, each cache including cache entries adapted to store data and status fields associated with the data, the status field representing the state of the data, eviction logic in the first cache adapted to test the status field of a cache entry, and control logic adapted to output the contents of the cache entry to a cache entry in the second cache when the status field indicates that data in the cache entry is dirty.

US Patent:

6401172, Jun 4, 2002

Filed:

Dec 18, 1998

Appl. No.:

09/215534

Inventors:

Chinna Prudvi - Portland OR
Derek T. Bachand - Portland OR
David L. Hill - Cornelius OR

Assignee:

Intel Corp. - Santa Clara CA

International Classification:

G00F 1812

US Classification:

711141, 711143, 711144, 711145, 711140

Abstract:

A method of processing a data request in a processing agent. The method comprises posting the data request internally within the agent and, if the data request implicates data associated with a pending external transaction, canceling and recycling the data request.

US Patent:

6412091, Jun 25, 2002

Filed:

May 4, 2001

Appl. No.:

09/848261

Inventors:

David L. Hill - Cornelius OR
Chinna Prudvi - Portland OR
Derek T. Bachand - Portland OR
Paul Breuder - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03M 1300

US Classification:

714785, 714746

Abstract:

An error correction system in an agent provides an error correction in a circuit path extending from an internal cache to an output of the agent. When data errors are detected for data to be processed internally within the agent, the error correction system passes the corrupted data through the error correction circuit, and out of the agent and back into the agent. The error correction changes internal data requests into an external transaction when data errors are detected.

US Patent:

6434677, Aug 13, 2002

Filed:

Jun 1, 1999

Appl. No.:

09/323360

Inventors:

Paul D. Breuder - Hillsboro OR
Derek T. Bachand - Portland OR
David Lawrence Hill - Cornelius OR
Chinna Prudvi - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711156, 711158, 711143, 711144, 711146, 711108, 711128

Abstract:

Increased efficiency in a multiple agent system is provided by allowing all explicit writebacks to continue during a snoop phase. Upon each incoming external bus request, an agent determines if the address of that request matches an address of data within the agent. If there is a match, the agent copies this most recent data, changes the state of the data to unmodified, changes the length of the data to zero (for pending explicit writebacks), and performs an implicit writeback. Additionally, prior to each explicit writeback, an agent determines if the address of the explicit writeback and any incoming snoop request requests are the same. If there is a match, the agent changes the data length of the explicit writeback to zero prior to issuing the explicit writeback.

US Patent:

6484239, Nov 19, 2002

Filed:

Dec 28, 1999

Appl. No.:

09/474012

Inventors:

David L. Hill - Cornelius OR
Chinna B. Prudvi - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1208

US Classification:

711137, 711213

Abstract:

A prefetching control system provided for a processor. The prefetching queue may include an arbiter, a cache queue and a prefetch queue. The arbiter issues requests including read requests. Responsive to a read request, the cache queue issues a control signal. The prefetch queue receives the control signal and an address associated with the read request. When the received address is a member of a pattern of read requests from sequential memory locations, the prefetch queue issues a prefetch request to the arbiter.

US Patent:

6557081, Apr 29, 2003

Filed:

Aug 29, 2002

Appl. No.:

10/230289

Inventors:

David L. Hill - Cornelius OR
Chinna B. Prudvi - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1208

US Classification:

711137, 711213

Abstract:

A prefetching control system provided for a processor. The prefetching queue may include an arbiter, a cache queue and a prefetch queue. The arbiter issues requests including read requests. Responsive to a read request, the cache queue issues a control signal. The prefetch queue receives the control signal and an address associated with the read request. When the received address is a member of a pattern of read requests from sequential memory locations, the prefetch queue issues a prefetch request to the arbiter.

US Patent:

6578114, Jun 10, 2003

Filed:

Jun 26, 2002

Appl. No.:

10/180009

Inventors:

Paul D. Breuder - Hillsboro OR
Derek T. Bachand - Portland OR
David Lawrence Hill - Cornelius OR
Chinna Prudvi - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

711141, 711144, 711146

Abstract:

Increased efficiency in a multiple agent system is provided by allowing all explicit writebacks to continue during a snoop phase. Upon each incoming external bus request, an agent determines if the address of that request matches an address of data within the agent. If there is a match, the agent copies this most recent data, changes the state of the data to unmodified, changes the length of the data to zero (for pending explicit writebacks), and performs an implicit writeback. Additionally, prior to each explicit writeback, an agent determines if the address of the explicit writeback and any incoming snoop request requests are the same. If there is a match, the agent changes the data length of the explicit writeback to zero prior to issuing the explicit writeback.

US Patent:

6654837, Nov 25, 2003

Filed:

Dec 28, 1999

Appl. No.:

09/474011

Inventors:

David L. Hill - Cornelius OR
Derek T. Bachand - Portland OR
Chinna B. Prudvi - Portland OR
Deborah T. Marr - Portland OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 1200

US Classification:

710200, 710220, 710240

Abstract:

A multi-mode transaction queue may operate according to a default priority scheme. When a congestion event is detected, the transaction queue may engage a second priority scheme.