Chinnappa K Ganapathy

US Patent:

7702712, Apr 20, 2010

Filed:

Dec 1, 2004

Appl. No.:

11/002478

Inventors:

Raghuraman Krishnamoorthi - San Diego CA, US
Chinnappa K. Ganapathy - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G06F 17/14

US Classification:

708404

Abstract:

A Fast Fourier Transform (FFT) hardware implementation and method provides efficient FFT processing while minimizing the die area needed in an Integrated Circuit (IC). The FFT hardware can implement an N point FFT, where N=ris a function of a radix (r). The hardware implementation includes a sample memory having N/r rows, each storing r samples. A twiddle factor memory can store k twiddle factors per row, where 0

US Patent:

8139612, Mar 20, 2012

Filed:

Apr 4, 2006

Appl. No.:

11/398156

Inventors:

Jinxia Bai - San Diego CA, US
Chinnappa K. Ganapathy - San Diego CA, US
Thomas Sun - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H04J 13/00
H04J 9/00
H04J 11/00
H04J 1/00

US Classification:

370479, 370204, 370206, 370484

Abstract:

Methods and apparatus for dynamic packet mapping. A method is provided for mapping metric data to produce a decodable packet associated with a channel. The method includes obtaining a channel identifier associated with metric data, determining an available buffer from a plurality of buffers based on the channel identifier, writing the metric data to the available buffer, detecting when a decodable packet is formed in a selected buffer of the plurality of buffers, and outputting the decodable packet from the selected buffer. An apparatus includes a plurality of buffers and mapping logic that is configured to obtain a channel identifier associated with metric data, determine an available buffer based on the channel identifier, write the metric data to the available buffer, detect when a decodable packet is formed in a selected buffer, and output the decodable packet from the selected buffer.

US Patent:

8213548, Jul 3, 2012

Filed:

Apr 4, 2006

Appl. No.:

11/398205

Inventors:

Jinxia Bai - San Diego CA, US
Chinnappa K. Ganapathy - San Diego CA, US
Thomas Sun - San Diego CA, US

Assignee:

Qualcomm Incorporated - San Diego CA

International Classification:

H04L 27/28
H04L 27/00
H04L 27/06
H04K 1/10

US Classification:

375340, 375260, 375316

Abstract:

Methods and apparatus for dynamic packet reordering. In an aspect, a method is provided for processing slot data on-the-fly to produce decodable packets, wherein the slot data includes interleaved modulation symbols. The method includes de-interleaving a stream of the interleaved modulation symbols to produce a stream of modulation symbols, calculating parallel streams of LLR metrics based on the stream of modulation symbols, and mapping the parallel streams of LLR metrics to produce a stream of decodable packets. In another aspect, an apparatus is provided the includes de-interleaving logic to de-interleave a stream of interleaved modulation symbols to produce a stream of modulation symbols, metric processing logic configured to produce parallel streams of LLR metrics based on the stream of modulation symbols, and mapping logic configured to map the parallel streams of LLR metrics to produce a stream of decodable packets.

US Patent:

8290069, Oct 16, 2012

Filed:

Oct 7, 2008

Appl. No.:

12/246998

Inventors:

Zhanfeng Jia - Belmont CA, US
David Jonathan Julian - San Diego CA, US
Qingjiang Tian - San Diego CA, US
James W. Dolter - San Diego CA, US
Vito R. Bica - Poway CA, US
Harinath Garudadri - San Diego CA, US
Chinnappa K. Ganapathy - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H04K 1/10
H04B 7/02

US Classification:

375260, 375267

Abstract:

A system and method for media access control are disclosed. The method comprises providing concurrent orthogonal channels to access media using pulse division multiple access to define pulse positions, wherein the pulse division multiple access includes a time hopping sequence and an offset to distinguish the concurrent orthogonal channels. In addition, the method comprises processing signals associated with at least one of the orthogonal channels.

US Patent:

8423852, Apr 16, 2013

Filed:

Jun 25, 2008

Appl. No.:

12/146301

Inventors:

Harinath Garudadri - San Diego CA, US
Somdeb Majumdar - San Diego CA, US
David Jonathan Julian - San Diego CA, US
Chinnappa K. Ganapathy - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H04L 1/00
G06F 11/00

US Classification:

714747, 714755, 714786, 714784, 714794, 714795

Abstract:

Low latency and computationally efficient techniques may be employed to account for errors in data such as low bit-width, oversampled data. In some aspects these techniques may be employed to mitigate audio artifacts associated with sigma-delta modulated audio data. In some aspects an error may be detected in a set of encoded data based on an outcome of a channel decoding process. Upon determining that a set of data may contain at least one error, the set of data may be replaced with another set of data that is based on one or more neighboring data sets. For example, in some aspects a set of data including at least one bit in error may be replaced with data that is generated by applying a cross-fading operation to neighboring data sets. In some aspects a given data bit may be flipped as a result of a linear prediction operation that is applied to PCM equivalent data that is associated with the given data bit and its neighboring data bits. In some aspects a set of data including at least one bit in error may be replaced with data that is generated by performing linear interpolation operations on PCM equivalent data that is associated with neighboring data sets.

US Patent:

8509859, Aug 13, 2013

Filed:

Mar 10, 2006

Appl. No.:

11/372876

Inventors:

Tadeusz Jarosinski - San Diego CA, US
Chinnappa K. Ganapathy - San Diego CA, US
Michael Mao Wang - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

H04B 1/16
H04B 1/38
H04M 1/00

US Classification:

455574, 4551275, 4553432, 4553435, 4553431

Abstract:

Disclosed are apparatus and methods for control of sleep modes in a transceiver or receiver. In particular, a transceiver is disclosed including a processor configured to determine timing information concerning sleep periods for at least a portion of components within the transceiver. The transceiver also includes a sleep control logic coupled to the processor to receive information concerning sleep periods from the processor and configured to effect shutting down of the at least a portion of the components of the transceiver during power reduction periods independent of the processor.

US Patent:

8543629, Sep 24, 2013

Filed:

Dec 18, 2006

Appl. No.:

11/612455

Inventors:

Jai N. Subrahmanyam - Santa Clara CA, US
Chinnappa K. Ganapathy - San Diego CA, US
Durk L. Van Veen - Santee CA, US
Jinxia Bai - San Diego CA, US
Kevin S. Cousineau - Ramona CA, US
Seokyong Oh - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G06F 17/14

US Classification:

708404, 708400

Abstract:

Techniques for perforating IFFT pipelining are described. In some aspects, the pipelining is achieved with a processing system having a memory with a first, second and third sections, an encoder configured to process data in each of the first, second and third memory sections in a round robin fashion, an IFFT configured to process the encoded data in each of the first, second, and third sections in a round robin fashion, and a post-processor configured to process the IFFT processed data in each of the first, second and third memory sections in a round robin fashion.

US Patent:

8589720, Nov 19, 2013

Filed:

May 9, 2008

Appl. No.:

12/118469

Inventors:

Harinath Garudadri - San Diego CA, US
Somdeb Majumdar - San Diego CA, US
Rouzbeh Kashef - La Jolla CA, US
Chinnappa K. Ganapathy - San Diego CA, US

Assignee:

QUALCOMM Incorporated - San Diego CA

International Classification:

G06F 1/04

US Classification:

713503, 713401

Abstract:

The rate at which data is provided by one device and the rate at which that data is processed by another device may differ. For example, a transmitting device may transmit data according to a transmit clock while a receiving device that receives the transmitted data may process the data according to a receive clock. If there is a timing mismatch between the transmit and receive clocks, the receiving device may receive data faster or slower than it processes the data. In such a case, there may be errors relating to the processing of the received data. To address timing mismatches such as this, the receiving device may delete data from or insert data into the received data. In conjunction with these operations, the receiving device may modify the received data at or near the insertion point or the deletion point in a manner that mitigates any adverse effect the insertion or deletion may have on a resulting output signal.