Chris R Baldwin

US Patent:

6362438, Mar 26, 2002

Filed:

Dec 15, 1999

Appl. No.:

09/461901

Inventors:

Tee Onn Chong - Chandler AZ
Chris Baldwin - Tempe AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H05K 111

US Classification:

174262, 174264, 361792

Abstract:

The present invention provides a circuit board with a plated-through hole, wherein a first end of the plated-through hole is electrically attached to a cap formed of conductive material. One or more surface pads terminate on a surface layer of the printed circuit board, and are connected to the cap by one or more vias extending from the cap to the one or more surface pads. In some embodiments, the circuit board is a substrate for mounting an integrated circuit, such as a ball-grid array integrated circuit. The invention includes methods for making the novel circuit board, as well as integrated circuit assemblies comprising the novel circuit board with an integrated circuit mounted thereto.

US Patent:

6777818, Aug 17, 2004

Filed:

Oct 24, 2001

Appl. No.:

10/045315

Inventors:

Chris Baldwin - Chandler AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2329

US Classification:

257795, 257692, 257724, 257789

Abstract:

An electronic package includes an IC, such as a die, mounted onto one side of a thin interposer and a pin carrier mounted to an opposing side of the interposer. The pin carrier includes a cavity underneath the die. The cavity allows capacitors, or other electronic components, to be mounted against the interposer beneath the die. The cavity in the pin carrier is filled with an encapsulant to mechanically support the thin interposer in the area of the cavity during operation of an electronic system that includes the package.

US Patent:

6784532, Aug 31, 2004

Filed:

Jul 31, 2002

Appl. No.:

10/209847

Inventors:

Dong Zhong - Chandler AZ
Farzaneh Yahyaei-Moayyed - Chandler AZ
David G. Figueroa - Mesa AZ
Chris Baldwin - Chandler AZ
Jiangqi He - Chandler AZ
Yuan-Liang Li - Chandler AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 2352

US Classification:

257691, 257668, 257692

Abstract:

An integrated circuit including a die, a power terminal and a ground terminal all mounted onto a substrate. The power terminal including a body and a first extension projecting from the body, and the ground terminal including a body and a second extension projecting from the body. The second extension on the ground terminal being adjacent to the first extension on the power terminal to offset inductance that is generated by supplying current to the die through the power terminal.

US Patent:

20040022038, Feb 5, 2004

Filed:

Jul 31, 2002

Appl. No.:

10/210391

Inventors:

David Figueroa - Mesa AZ, US
Chris Baldwin - Chandler AZ, US
Yuan-Liang Li - Chandler AZ, US

Assignee:

Intel Corporation

International Classification:

H05K007/06
H01L023/58

US Classification:

361/763000, 361/761000, 257/724000

Abstract:

An electronic package, such as an integrated circuit package, includes a cavity (FIGS. ) on the back side of the package, which is the same side on which connectors (FIGS. ) to a next level of interconnect are located. Within the cavity are contacts (FIGS. ), which enable one or more discrete capacitors (FIGS. ) to be electrically connected to the package. The package provides a very low vertical inductance path between the capacitors and an integrated circuit (FIG. ) mounted on the front side of the package.

US Patent:

20040241914, Dec 2, 2004

Filed:

Jul 2, 2004

Appl. No.:

10/884654

Inventors:

Chris Baldwin - Chandler AZ, US

Assignee:

Intel Corporation

International Classification:

H01L023/48
H01L021/44
H01L021/50
H01L021/48
H01L023/52

US Classification:

438/126000, 438/127000

Abstract:

An electronic package includes an IC, such as a die, mounted onto one side of a thin interposer and a pin carrier mounted to an opposing side of the interposer. The pin carrier includes a cavity underneath the die. The cavity allows capacitors, or other electronic components, to be mounted against the interposer beneath the die. The cavity in the pin carrier is filled with an encapsulant to mechanically support the thin interposer in the area of the cavity during operation of an electronic system that includes the package.

US Patent:

20050127489, Jun 16, 2005

Filed:

Dec 10, 2003

Appl. No.:

10/733183

Inventors:

Debendra Mallik - Chandler AZ, US
Chris Baldwin - Chandler AZ, US
Brent Stone - Chandler AZ, US

International Classification:

H01L021/48
H01L023/02

US Classification:

257686000, 438109000, 257778000, 438108000

Abstract:

A microelectronic device package including an electrically conductive lid having an attachment surface, a substrate having an attachment surface, at least one interconnect extending between the lid attachment surface and the substrate attachment surface, at least one microelectronic die disposed between the lid attachment surface and the substrate attachment surface, and the substrate having at least one first conductive trace extending between the electrically conductive first interconnect and the microelectronic die. The microelectronic device package allows for the use of the electrically conductive lid as a path for conducting signals (preferably power or ground) to and/or from a microelectronic die.

US Patent:

20140158414, Jun 12, 2014

Filed:

Dec 11, 2012

Appl. No.:

13/711092

Inventors:

CHRIS BALDWIN - CHANDLER AZ, US
MIHIR K. ROY - CHANDLER AZ, US

International Classification:

H05K 1/18
H05K 3/30

US Classification:

174260, 29832

Abstract:

A method and device include an organic multiple layer substrate having patterned conductors disposed on a recessed layer of the organic multiple layer substrate. A discrete component is coupled to the recessed layer such that the component is recessed from a top layer of the organic multiple layer substrate.