Chris A Cooper

US Patent:

6917228, Jul 12, 2005

Filed:

Jun 6, 2002

Appl. No.:

10/164735

Inventors:

Chris Cooper - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H03L007/06

US Classification:

327158, 327159, 331DIG 2, 375376

Abstract:

A delay locked loop circuit has a quantifier for obtaining a measured delay quantity based on a time delay between an external signal and an internal signal. Based on the measured delay quantity, a delay controller controls a correction delay quantity applied to a signal path of the external signal to synchronize the external and internal signals.

US Patent:

6986084, Jan 10, 2006

Filed:

Jun 29, 2004

Appl. No.:

10/879437

Inventors:

Chris Cooper - Boise ID, US
Siang Tian Giam - Singapore, SG
Jerry D. McBride - Biose ID, US
Scott N. Gatzemeier - Boise ID, US
Scott L. Ayres - Meridian ID, US
David R. Brown - Allen TX, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 29/00

US Classification:

714719, 365201

Abstract:

An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.

US Patent:

7119592, Oct 10, 2006

Filed:

Aug 31, 2004

Appl. No.:

10/931843

Inventors:

Chris Cooper - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H03L 7/00

US Classification:

327158, 327161

Abstract:

A delay locked loop circuit has a quantifier for obtaining a measured delay quantity based on a time delay between an external signal and an internal signal. Based on the measured delay quantity, a delay controller controls a correction delay quantity applied to a signal path of the external signal to synchronize the external and internal signals.

US Patent:

20040255211, Dec 16, 2004

Filed:

May 25, 2004

Appl. No.:

10/853573

Inventors:

Chris Cooper - Boise ID, US
Siang Giam - Singapore, SG
Jerry McBride - Boise ID, US
Scott Gatzemeier - Boise ID, US
Scott Ayres - Meridian ID, US
David Brown - Allen TX, US

International Classification:

G11C007/00
G11C029/00

US Classification:

714/726000, 714/718000

Abstract:

An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.

US Patent:

20070168790, Jul 19, 2007

Filed:

Jun 2, 2006

Appl. No.:

11/445944

Inventors:

Chris Cooper - Boise ID, US
Siang Giam - Singapore, SG
Jerry McBride - Boise ID, US
Scott Gatzemeier - Boise ID, US
Scott Ayres - Meridian ID, US
David Brown - Allen TX, US

International Classification:

G01R 31/28

US Classification:

714724000

Abstract:

An apparatus and a method are disclosed for reducing the pin driver count required for testing computer memory devices, specifically Rambus DRAM, while a die is on a semiconductor wafer. By reducing the pin count, more DRAMs can be tested at the same time, thereby reducing test cost and time. One preferred embodiment utilizes a trailing edge of a precharge clock to select a new active bank address, so that the address line required to select a new active address does not have to be accessed at the same time as the row lines.