Chris M Demarco

US Patent:

20110032006, Feb 10, 2011

Filed:

Feb 24, 2010

Appl. No.:

12/712025

Inventors:

PRASHANT SHAMARAO - Duluth GA, US
Chris Demarco - Alpharetta GA, US
Rohit Singhal - Duluth GA, US
Robert Bishop - Suwanee GA, US
Alex Reed - Atlanta GA, US

International Classification:

H03B 1/00

US Classification:

327108

Abstract:

An AUX channel amplifier for amplifying data in the AUX channel of a Display Port device. In some embodiments, the amplifier includes a first amplifier coupled to amplify a signal from a source to a sink and a second amplifier coupled to amplify a signal from the sink to the source. A slicer can be utilized to digitize the signal from the source. In some embodiments, a clock and data recovery can be utilized to receive signals from the source and a second clock and data recovery can be utilized to receive signals from the sink. A controller determine the direction of data flow and enables the first amplifier or the second amplifier accordingly.

US Patent:

20120038398, Feb 16, 2012

Filed:

Aug 11, 2010

Appl. No.:

12/854702

Inventors:

Rohit Singhal - Duluth GA, US
Chris DeMarco - Alpharetta GA, US

Assignee:

INTEGRATED DEVICE TECHNOLOGY, INC. - San Jose CA

International Classification:

H03L 7/00

US Classification:

327153

Abstract:

Clock-domain-crossing systems and methods include an integrator that accumulates input samples over multiple clock cycles in a first clock domain to generate an accumulation result. Clock-domain-crossing circuitry samples the accumulation result in the first clock domain after each of a repeating accumulation count to generate a first domain accumulation. The first domain accumulation is sampled in a second clock domain after a time delay to generate a second domain accumulation. The time delay ensures proper setup and hold time parameters for the second clock domain relative to the first clock domain. A differentiator generates output information in the second clock domain by delaying the second domain accumulation and subtracting the delayed second domain accumulation from the second domain accumulation. The systems and methods preserve temporal characteristics of the input information in the first clock domain when it is transferred to the second clock domain as the output information.