Chris A Larsen

Address:

167 E Burney Gln Ct, Meridian, ID 83646

VIN:

4X4TFLU277D093248

Make:

BMW

Model:

X5-Series AWD 4dr 4.8i

Year:

2007

US Patent:

7824994, Nov 2, 2010

Filed:

Nov 14, 2008

Appl. No.:

12/271132

Inventors:

Kirk Prall - Boise ID, US
Behnam Moradi - Haymarket VA, US
Seiichi Aritome - Boise ID, US
Di Li - Boise ID, US
Chris Larsen - Manassas VA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/336

US Classification:

438301, 257E21248

Abstract:

Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

US Patent:

8129781, Mar 6, 2012

Filed:

Sep 28, 2010

Appl. No.:

12/892691

Inventors:

Kirk D Prall - Boise ID, US
Behnam Moradi - Boise ID, US
Seiichi Aritome - Boise ID, US
Di Li - Boise ID, US
Chris Larsen - Manassas VA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/336

US Classification:

257336, 438301

Abstract:

Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

US Patent:

8415223, Apr 9, 2013

Filed:

Feb 3, 2012

Appl. No.:

13/365472

Inventors:

Kirk D. Prall - Boise ID, US
Behnam Moradi - Boise ID, US
Seiichi Aritome - Boise ID, US
Di Li - Highland CA, US
Chris Larsen - Manassas VA, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/336

US Classification:

438301, 257E21248

Abstract:

Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.

US Patent:

8450789, May 28, 2013

Filed:

Aug 24, 2010

Appl. No.:

12/862107

Inventors:

Andrew Bicksler - Boise ID, US
Chris Larsen - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 29/788

US Classification:

257315, 257316, 257E21422

Abstract:

Memory arrays and their formation are disclosed. One such memory array has first and second memory cells over a semiconductor, an air gap between the first and second memory cells, and an isolation region within the semiconductor and under the air gap so that the isolation region is aligned with the air gap.

US Patent:

20080014698, Jan 17, 2008

Filed:

Jul 14, 2006

Appl. No.:

11/457620

Inventors:

Kirk Prall - Boise ID, US
Behnam Moradi - Haymarket VA, US
Seiichi Aritome - Boise ID, US
Di Li - Boise ID, US
Chris Larsen - Manassas VA, US

International Classification:

H01L 21/336

US Classification:

438257

Abstract:

Disclosed is a method of forming memory devices employing halogen ion implantation and diffusion processes. In one illustrative embodiment, the method includes forming a plurality of word line structures above a semiconducting substrate, each of the word line structures comprising a gate insulation layer, performing an LDD ion implantation process to form LDD doped regions in the substrate between the word line structures, performing a halogen ion implantation process to implant atoms of halogen into the semiconducting substrate between the word line structures, and performing at least one anneal process to cause at least some of the atoms of halogen to diffuse into the gate insulation layers on adjacent word line structures.