Chris M Stone

US Patent:

6516420, Feb 4, 2003

Filed:

Oct 25, 1999

Appl. No.:

09/426265

Inventors:

Srinath Audityan - Austin TX
Chris Randall Stone - Austin TX
Ritesh Radheshyam Agrawal - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1342

US Classification:

713400, 375370, 327145

Abstract:

A data synchronizer transfers information across an asynchronous interface by using system domain and core domain logic on either side of the asynchronous interface. Information registers receive data beats from a data bus coupled to an external system. Each data beat is loaded into the registers in sequential order. A corresponding system valid bit is provided for each register and is set when the corresponding register is loaded. In the core domain, a corresponding set of core valid bit registers is set in response to the system valid bit registers being set. A data sampler monitors the core valid bits in sequential order and controls a multiplexor to select a corresponding one of the registers that contains valid data. The data sampler resets the core valid bits which in-turn reset the system valid bits to signal the completion of a data transfer across the asynchronous interface.

US Patent:

20080072118, Mar 20, 2008

Filed:

Aug 31, 2006

Appl. No.:

11/468838

Inventors:

David A. Brown - Austin TX, US
James Thomas Kirk - Austin TX, US
David P. Sonnier - Austin TX, US
Chris R. Stone - Austin TX, US

International Classification:

G11C 29/00

US Classification:

714763

Abstract:

In a system including a processor and memory coupled to the processor, a method of device failure analysis includes the steps of: upon each error detected within a test series performed on a device, the processor storing within a table in the memory an address at which the error occurred in the device and storing a bit position of each failed bit corresponding to that address; for each unique address at which at least one error occurred, determining how many different bit positions corresponding to the address failed during the test series; and based on results of the test series, determining whether the device failed the test series.

US Patent:

20120084498, Apr 5, 2012

Filed:

Dec 9, 2011

Appl. No.:

13/316145

Inventors:

David Sonnier - Austin TX, US
Chris Randall Stone - Austin TX, US

International Classification:

G06F 12/00
G06F 12/08
G06F 9/30

US Classification:

711105, 712 4, 711118, 711141, 712E09023, 711E12026

Abstract:

Described embodiments provide a method of controlling processing flow in a network processor having one or more processing modules. A given one of the processing modules loads a script into a compute engine. The script includes instructions for the compute engine. The given one of the processing modules loads a register file into the compute engine. The register file includes operands for the instructions of the loaded script. A tracking vector of the compute engine is initialized to a default value, and the compute engine executes the instructions of the loaded script based on the operands of the loaded register file. The compute engine updates corresponding portions of the register file with updated data corresponding to the executed script. The tracking vector tracks the updated portions of the register file. The compute engine provides the tracking vector and the updated register file to the given one of the processing modules.

US Patent:

6389489, May 14, 2002

Filed:

Mar 17, 1999

Appl. No.:

09/271215

Inventors:

Chris Randall Stone - Austin TX
Ritesh Radheshyam Agrawal - Austin TX

Assignee:

Motorola, Inc. - Schaumburg IL

International Classification:

G06F 1300

US Classification:

710 57, 710 52, 711109, 365221

Abstract:

A data processor ( ) includes a first-in, first-out (FIFO) buffer ( ) having a variable threshold. The FIFO buffer ( ) has a plurality of entries ( ) for storing at least a portion of a data block that is to be transmitted through the FIFO buffer ( ). To allow data blocks of varying size to be transmitted at different data rates, a variable threshold value for determining a maximum fullness of the FIFO buffer ( ) is automatically calculated by the data processor ( ) for each data block. This allows the data block to be transmitted through the FIFO buffer ( ) as a continuous data stream, without interruption, from the data processor ( ) to a data consumer. The variable threshold value is appended to a first entry of the data block along with start bits to indicate a beginning of the data block. The FIFO buffer ( ) may include read and write counters ( ) and a comparator ( ) for comparing a difference between read and write pointers and the variable threshold value.

Address:

3812 Brookview Rd, Austin, TX 78722

VIN:

4S4BRCCC4A3338454

Make:

SUBARU

Model:

OUTBACK

Year:

2010