Tax Supervising Senior Accountant at SingerLewak LLP
Location:
San Francisco Bay Area
Industry:
Accounting
Work:
SingerLewak LLP - San Jose, CA since Jan 2011
Tax Supervising Senior Accountant
Weil & Company, LLP - Los Angeles, CA Aug 2007 - Jan 2011
Senior Accountant
Starz Lacrosse LLC - Manhattan Beach, CA Mar 2006 - Aug 2007
Accountant
Los Angeles Business Council - Los Angeles, CA Jul 2004 - Mar 2006
Intern
Education:
Loyola Marymount University, College of Business Administration 2003 - 2007
Bachelor of Science, Accounting
Veeva Systems
Product Designer
Sencha Feb 2016 - Sep 2017
Product Designer
Pandora House Mar 2014 - Dec 2015
Graphic Designer and Animator
Education:
General Assembly 2015 - 2015
Cal State East Bay - College of Business & Economics 2011 - 2014
Bachelors, Business Administration, Marketing, Art, Multimedia
Skills:
Illustrator Photoshop User Interface Design Graphic Design After Effects User Experience Design Animation Rapid Prototyping Adobe Creative Suite Wireframes Information Architecture Sketching Logo Design User Research 3D Modeling Character Animation Usability Testing Game Design Web Design Video Games Agile Methodologies Paper Prototyping Storyboarding Digital Illustration Omnigraffle Maya Indesign Sketch Interaction Design Mental Models Layout Microsoft Office Task Analysis User Flows Usability Gameplay Computer Animation Javascript Powerpoint Microsoft Word Dreamweaver Visual Design Heuristic Analysis Trend Analysis Axure Rp Video Editing Invision Processing Unity3D Cinema 4D
Interests:
Education Environment Poverty Alleviation Science and Technology Human Rights Animal Welfare Arts and Culture Health
Hai Dau - San Ramon CA, US Lim Hooi Weng - Singapore, SG Kothandan Shanmugam - Singapore, SG Christine Bui - Gilroy CA, US
International Classification:
G01R 31/28 G01R 1/067
Abstract:
In one embodiment, the present invention includes an interface apparatus for semiconductor testing. The interface apparatus comprises a housing substrate and two product substrates. The first product substrate has a first micro-scale conductive pattern and is situated within a first opening of the housing substrate. The second product substrate has a second micro-scale conductive pattern and is situated within a second opening of the housing substrate. The first and the second micro-scale conductive patterns are aligned to a conductive semiconductor wafer pattern using a continuous translucent media having targets corresponding to the conductive semiconductor wafer pattern.
Interface Apparatus For Semiconductor Testing And Method Of Manufacturing Same
Hai Dau - San Ramon CA, US Lim Hooi Weng - Singapore, SG Kothandan Shanmugam - Singapore, SG Christine Bui - Gilroy CA, US
International Classification:
H01R 27/02 H01R 43/20 H01R 43/02
Abstract:
In one embodiment, the present invention includes an interface apparatus for semiconductor testing. The interface apparatus includes a housing. The housing includes a lower housing substrate and an upper housing substrate. The lower housing substrate has a plurality of apertures arranged according to a fine pitch, and the upper housing substrate has a plurality of apertures arranged according to a coarse pitch. A plurality of wires passes through the plurality of apertures from the lower housing substrate to the upper housing substrate. Each wire has plated conductive ends emanating from opposing sides of the housing. The plurality of apertures of the lower housing substrate corresponds to the plurality of apertures of the upper housing substrate. The interface apparatus transforms a pattern having a course pitch to a pattern having a fine pitch.