Christopher G Arcus

US Patent:

6426662, Jul 30, 2002

Filed:

Nov 12, 2001

Appl. No.:

09/683040

Inventors:

Christopher G. Arcus - San Jose CA

Assignee:

Pericom Semiconductor Corp. - San Jose CA

International Classification:

G06F 104

US Classification:

327295, 327274, 331 57

Abstract:

A phase-locked loop (PLL) or a delay-locked loop (DLL) has differential delay stages with differential outputs driving differential clock inputs to a pair of differential toggle flip-flops. One flip-flop changes state on the rising edge and the other on the falling edge of the true output from the delay stage. Differential-to-single-ended buffers convert differential flip-flop outputs to single-ended multi-phase clocks. To avoid erratic or multiple oscillation and overtones, fewer than eight and preferably four differential delay stages are used. The delay stages are arranged in a twisted-ring with the differential outputs of the last delay stage crossed over and fed back to the differential inputs of the first delay stage. Tail currents of the delay stages can be adjusted by a voltage generated by a PLL loop. The differential toggle flip-flops allow for many taps or clock phases to be generated from the few delay stages.

US Patent:

6801080, Oct 5, 2004

Filed:

Apr 7, 2003

Appl. No.:

10/249414

Inventors:

Christopher G. Arcus - San Jose CA

Assignee:

Pericom Semiconductor Corp. - San Jose CA

International Classification:

G06G 726

US Classification:

327563, 327379, 330253

Abstract:

A differential input buffer shows reduced sensitivity to input conditions such as input-trace loading and upstream driver characteristics. Varying input conditions can be measured as differences in amplitude, slew rate, and common-mode offset. Wide input-voltage swings are clamped to a limited voltage range by an input clamp circuit that uses source followers to drive p-channel clamp transistors that turn off when the input voltage is too low. A voltage divider then sets the lowest voltage input to a differential stage. The differential stage receives the clamped inputs and has two tail current sinks to reduce delay sensitivity to charging and discharging of tail capacitances. A middle voltage is applied to transistors opposite the differential transistors that receive the clamped input voltages. A bias voltage for the tail current sinks is generated by mirroring currents and setting a gate voltage by injecting and removing a same bias current from a resistor.

US Patent:

7132835, Nov 7, 2006

Filed:

Feb 7, 2003

Appl. No.:

10/248683

Inventors:

Christopher G. Arcus - San Jose CA, US

Assignee:

Pericom Semiconductor Corp. - San Jose CA

International Classification:

G01R 31/08
G01R 31/14

US Classification:

324523, 324548, 324509

Abstract:

A filter capacitor within a phase-locked loop (PLL) can be tested using a built-in test circuit. The PLL's charge pump is deactivated while a test-current source is activated to supply a test current to the PLL filter capacitor. When the test current is larger than any leakage currents through the capacitor, the capacitor's voltage rises above a reference voltage. A test comparator compares the capacitor's voltage to the reference voltage and signals a good test result when the capacitor's voltage rises above the reference voltage. When leakage current is larger than the test current, the capacitor's voltage cannot rise above the reference voltage and the test comparator signal a leakage failure. The test current source can share a bias voltage with the charge pump and can drive the capacitor to a voltage higher than the charge pump does to increase leakage and stress during testing.

US Patent:

7834672, Nov 16, 2010

Filed:

Feb 10, 2007

Appl. No.:

11/673569

Inventors:

Christopher G. Arcus - San Jose CA, US
Vincent Tso - Milpitas CA, US
James Ho - San Jose CA, US

Assignee:

Exar Corporation - Fremont CA

International Classification:

H03L 7/06

US Classification:

327157

Abstract:

A charge pump is configured to control current flow at an output node in response to input signals. A plurality of control signals are generated based upon the input signals. The control signals operate to control the timing and duration of current flows within the charge pump and to thereby reduce charge pump power consumption. Based upon the control signals, the conductivity of a first path between a power supply and the output node and a second path between the output node and a ground potential is varied. Optionally, the charge pump is disposed as part of a phase-locked loop (PLL), the input signals are produced by a phase/frequency detector, and current flow at the output node controls an oscillator element.

US Patent:

55150128, May 7, 1996

Filed:

May 17, 1995

Appl. No.:

8/442850

Inventors:

Bharat Bhushan - Cupertino CA
Christopher G. Arcus - San Jose CA
Paul D. Ta - San Jose CA

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

H03B 504
H03L 7099

US Classification:

331 17

Abstract:

A ring-style, multi-stage VCO of a phase lock loop circuit includes two or more differential amplifier stages. The phase lock loop includes a lowpass filter connected between a control voltage terminal and a voltage-to-current converter stage, which includes a first source-follower MOS transistor M1 with a source resistor R1 and a second diode-connected MOS transistor M2 connected to its drain terminal. A differential amplifier stage includes a current-source MOS transistor M10 having a gate terminal connected to the drain of the first MOS transistor M1 to current mirror the drain current of M1. The differential amplifier stage also includes a pair of MOS transistors M4 and M5 connected to the drain terminal of the current-source MOS transistor M10. The gate terminal of MOS transistor M4 is an IN terminal and the gate terminal of MOS transistor M5 is an IN. sub. -- terminal.

US Patent:

48765171, Oct 24, 1989

Filed:

Jun 17, 1988

Appl. No.:

7/208290

Inventors:

Christopher G. Arcus - San Jose CA

Assignee:

Ixys Corporation - San Jose CA

International Classification:

H03F 316

US Classification:

330277

Abstract:

A current sensing circuit includes a pair of power devices connected in parallel. The mirror terminal of the first power device is coupled to a small sense resistance, and the mirror terminal of the second power device is connected to a large sense resistance. Each mirror terminal is coupled to its own comparator. Small currents are sensed by the comparator coupled to the mirror terminal of the first power device, and large currents are sensed by the comparator coupled to the mirror terminal of the second power device. If multiple mirror terminals are not available, a large sense resistance may be connected to the mirror terminal of the power device, and a small sense resistance may be selectively connected in parallel with the large resistance to provide low current-sensing capabilities. Accuracy of the device is enhanced by circuitry which minimizes the effect of integrated impedance variation and a variation in the low sense resistances.

US Patent:

61247413, Sep 26, 2000

Filed:

Mar 8, 1999

Appl. No.:

9/264284

Inventors:

Christopher G. Arcus - San Jose CA

Assignee:

Pericom Semiconductor Corp. - San Jose CA

International Classification:

H03K 300

US Classification:

327112

Abstract:

A more accurate charge pump reduces phase error in a PLL. An UP input pulse causes a p-channel drive transistor to charge a filter capacitor on the output, while a down DN input pulse causes an n-channel drive transistor to discharge the output. The drive transistors are connected to power or ground through a supply transistor. The supply transistor is biased on in the linear region and is not switched off. The sources of the drive transistors are always driven by the supply transistors, preventing phase error from floating sources. The drive transistors are common-gate switches with their gates biased by a compensating bias generator. The p-channel drive transistor current variations with Vds are compensated by providing a similar current variation to the n-channel drive transistor. Thus the bias is adjusted to compensate for drain-source voltage changes that can cause the up and down currents from the drive transistors to mismatch. The drive transistors are switched on and off by the up and down input pulses by current sources that steer additional current through the supply transistors.

US Patent:

55237231, Jun 4, 1996

Filed:

May 17, 1995

Appl. No.:

8/443131

Inventors:

Christopher G. Arcus - San Jose CA
Bharat Bhushan - Cupertino CA
Paul D. Ta - San Jose CA

Assignee:

VLSI Technology, Inc. - San Jose CA

International Classification:

H03B 504
H03L 7099

US Classification:

331 17

Abstract:

A ring-style, multi-stage VCO of a phase lock loop circuit includes two or more differential amplifier stages. The phase lock loop includes a lowpass filter connected between a control voltage terminal and a voltage-to-current converter stage, which includes a first source-follower MOS transistor M1 with a source resistor R1 and a diode-connected MOS transistor M2 connected to its drain terminal. A current-source MOS transistor M8 has a gate terminal connected to the drain of the first MOS transistor M1 such that the transistor M8 mirrors current of transistor M1. A diode-connected transistor M9 has its gate terminal and its drain terminal connected together and also to the drain terminal of transistor M8. A differential amplifier stage includes a current-source MOS transistor M10 having a gate terminal connected to the drain of the first MOS transistor M1 to current mirror the drain current of M1. The differential amplifier stage also includes a pair of MOS transistors M4 and M5 connected to the drain terminal of the current-source MOS transistor M10.