Christopher R Clark

US Patent:

7093224, Aug 15, 2006

Filed:

Aug 28, 2001

Appl. No.:

09/941158

Inventors:

William R. Wheeler - Southborough MA, US
Matthew J. Adiletta - Worcester MA, US
Christopher Clark - Hopkinton MA, US
Timothy J. Fennel - Holliston MA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 17/50

US Classification:

716 18

Abstract:

A technique for designing a logic circuit includes specifying a model. The model including combinatorial blocks, state elements and graphical library elements. The technique maintains a data structure representative of the model, and generates an architectural model and an implementation model from the data structure. The data structure represents a descriptive net list of the model. The architectural model includes C++ code and the implementation model includes Verilog.

US Patent:

8325069, Dec 4, 2012

Filed:

Dec 22, 2009

Appl. No.:

12/645392

Inventors:

Vinodh Gopal - Westborough MA, US
Gilbert M. Wolrich - Framingham MA, US
Christopher F. Clark - Chandler AZ, US
Wadji K. Feghali - Boston MA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03M 7/34
H03M 7/38

US Classification:

341 51, 341 65, 341 67, 341 87

Abstract:

Systems, methods, and apparatus for a scalable processor architecture for variety of string processing application are described. In one such apparatus, n input first in, first out (FIFO) buffer stores an input stream. A plurality of memory banks store data from the input stream. A re-configurable controller processes the input stream. And an output FIFO buffer stores the processed input stream.

US Patent:

20100169401, Jul 1, 2010

Filed:

Dec 30, 2008

Appl. No.:

12/346734

Inventors:

VINODH GOPAL - Westboro MA, US
Christopher F. Clark - Hopkinton MA, US
Gilbert Wolrich - , US
Wajdi Feghali - Boston MA, US

International Classification:

G06F 17/10

US Classification:

708316, 708300

Abstract:

Methods and apparatus to perform string matching for network packet inspection are disclosed. In some embodiments there is a set of string matching slice circuits, each slice circuit of the set being configured to perform string matching steps in parallel with other slice circuits. Each slice circuit may include an input window storing some number of bytes of data from an input data steam. The input window of data may be padded if necessary, and then multiplied by a polynomial modulo an irreducible Galois-field polynomial to generate a hash index. A storage location of a memory corresponding to the hash index may be accessed to generate a slice-hit signal of a set of H slice-hit signals. The slice-hit signal may be provided to an AND-OR logic array where the set of H slice-hit signals is logically combined into a match result.

US Patent:

D3652130, Dec 19, 1995

Filed:

Jan 9, 1995

Appl. No.:

D/033269

Inventors:

Christopher W. Clark - Wellesley MA

US Classification:

D 6380