Christopher B Clark

US Patent:

7093224, Aug 15, 2006

Filed:

Aug 28, 2001

Appl. No.:

09/941158

Inventors:

William R. Wheeler - Southborough MA, US
Matthew J. Adiletta - Worcester MA, US
Christopher Clark - Hopkinton MA, US
Timothy J. Fennel - Holliston MA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 17/50

US Classification:

716 18

Abstract:

A technique for designing a logic circuit includes specifying a model. The model including combinatorial blocks, state elements and graphical library elements. The technique maintains a data structure representative of the model, and generates an architectural model and an implementation model from the data structure. The data structure represents a descriptive net list of the model. The architectural model includes C++ code and the implementation model includes Verilog.

US Patent:

8325069, Dec 4, 2012

Filed:

Dec 22, 2009

Appl. No.:

12/645392

Inventors:

Vinodh Gopal - Westborough MA, US
Gilbert M. Wolrich - Framingham MA, US
Christopher F. Clark - Chandler AZ, US
Wadji K. Feghali - Boston MA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H03M 7/34
H03M 7/38

US Classification:

341 51, 341 65, 341 67, 341 87

Abstract:

Systems, methods, and apparatus for a scalable processor architecture for variety of string processing application are described. In one such apparatus, n input first in, first out (FIFO) buffer stores an input stream. A plurality of memory banks store data from the input stream. A re-configurable controller processes the input stream. And an output FIFO buffer stores the processed input stream.

US Patent:

8484147, Jul 9, 2013

Filed:

Dec 19, 2008

Appl. No.:

12/340360

Inventors:

Christopher F. Clark - Berlin MA, US
Vinodh Gopal - Westborough MA, US
Gilbert M. Wolrich - Framingham MA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 17/00
G06N 5/02

US Classification:

706 46

Abstract:

A method and apparatus to perform pattern matching is provided. The apparatus includes a first storage to store data representing a first set of pattern components, and a second storage to store data representing a second set of pattern components each corresponding to one or more components of the first set of pattern components. A first pattern matcher is configured to detect in an input stream a first component of one or more patterns and to generate a signal indicative of the detection of the first component. A second pattern matcher is configured to receive the signal from the first pattern matcher and to detect if a second component of the one or more patterns of the set of patterns immediately follows the first component in the input stream.

US Patent:

20090174551, Jul 9, 2009

Filed:

Jan 7, 2008

Appl. No.:

12/008099

Inventors:

William Vincent Quinn - Crofton MD, US
Christopher Joseph Clark - North Potomac MD, US
Robert William Pearson - Rockville MD, US
Andrey Sergeevich Mikhalchuk - Germantown MD, US

International Classification:

G08B 21/00
G06F 15/16
H04L 9/32
G06Q 30/00

US Classification:

340540, 709224, 726 1, 705 1

Abstract:

Methods and apparatus for evaluating Internet activity are disclosed. One embodiment of the invention pertains to a child using the Internet and a parent inspecting said child's activity on the Internet, which enables said parent to intervene if said child's Internet activity is inappropriate.

US Patent:

20100169401, Jul 1, 2010

Filed:

Dec 30, 2008

Appl. No.:

12/346734

Inventors:

VINODH GOPAL - Westboro MA, US
Christopher F. Clark - Hopkinton MA, US
Gilbert Wolrich - , US
Wajdi Feghali - Boston MA, US

International Classification:

G06F 17/10

US Classification:

708316, 708300

Abstract:

Methods and apparatus to perform string matching for network packet inspection are disclosed. In some embodiments there is a set of string matching slice circuits, each slice circuit of the set being configured to perform string matching steps in parallel with other slice circuits. Each slice circuit may include an input window storing some number of bytes of data from an input data steam. The input window of data may be padded if necessary, and then multiplied by a polynomial modulo an irreducible Galois-field polynomial to generate a hash index. A storage location of a memory corresponding to the hash index may be accessed to generate a slice-hit signal of a set of H slice-hit signals. The slice-hit signal may be provided to an AND-OR logic array where the set of H slice-hit signals is logically combined into a match result.

US Patent:

20120024784, Feb 2, 2012

Filed:

May 11, 2011

Appl. No.:

13/105149

Inventors:

Christopher Clark - Madeira Beach FL, US
Joseph Bonazza - Tarentum PA, US
Navin Kadakia - Bridgeville PA, US
Peter Ritchey - Mount Lebanon PA, US
Richard Dennis - Wesley Chapel FL, US

International Classification:

C02F 1/20
C02F 1/44
C02F 1/66
B01D 69/08
B01D 61/00

US Classification:

210638, 210151, 210137, 210 88

Abstract:

Apparatuses, systems and processes for fluid gasification and degasification are disclosed. A fluid gasification/degasification apparatus includes housing having a central axis and at least one fluid inlet and at least one fluid outlet positioned at different axial locations along the housing. A membrane unit that includes a plurality of bundled microporous hollow membrane strands is disposed within the housing and extends in parallel to the central axis of the housing. The fluid gasification/degasification apparatus further includes one or more gas addition/removal apparatuses for facilitating at least one of: a gas addition operation and a gas removal operation. An orientation of the fluid inlet(s) and fluid outlet(s) results in a substantial portion of a carrier fluid introduced to the housing traveling in parallel along exterior surfaces of the membrane unit thereby allowing for an extended interface time between the carrier fluid and micro-bubbles of a gas supplied to the membrane unit.

US Patent:

20140076817, Mar 20, 2014

Filed:

Sep 17, 2012

Appl. No.:

13/621355

Inventors:

Richard Dennis - Wesley Chapel FL, US
Christopher Clark - Madeira Beach FL, US

Assignee:

SEVERN TRENT WATER PURIFICATION, INC. - Colmar PA

International Classification:

C02F 1/42

US Classification:

210677, 210275

Abstract:

Embodiments of the present invention provide systems and methods for purifying produced water, comprising a closed loop cation exchange unit, a closed loop anion exchange unit, and an intermediate degasifier.

US Patent:

54681650, Nov 21, 1995

Filed:

Sep 13, 1994

Appl. No.:

8/305256

Inventors:

David R. Weber - Belleair FL
Christopher S. Clark - Indian Rocks Beach FL

Assignee:

D. R. Weber, Inc. - Belleair FL

International Classification:

B63H 1101

US Classification:

440 46

Abstract:

A passive anti-clogging device for feeding water into marine jet pumps, which displaces the laminar flow around the trailing surfaces of the intake port, such that foreign debris and grass are precluded from clogging the intake to the jet pump. The primary component of the invention comprises an exclusion plate that is placed in, or immediately below the intake port, and affixed to the breadth of, or becoming a part of, the trailing edge of the intake port, leaving an opening, or slot, between the exclusion plate and ride plate, or bottom of the vessel, which, when at rest, allows the passage of water only from its anterior and lateral extents, thereby excluding the flow of water into the device from directly below or behind the plate. The edge of the exclusion plate angles or curves from a forward central point or apex to a back point at the trailing edge of the intake port, providing a fair surface to resist laminar attachment of debris, marine vegetation or other debris.

Address:

9440 Leatherwood Ave, Tampa, FL 33647

VIN:

WBANU535X8CT09609

Make:

BMW

Model:

5 SERIES

Year:

2008

Address:

9249 Dayflower Dr, Tampa, FL 33647

VIN:

JTMZD32V776041710

Make:

TOYOTA

Model:

RAV4

Year:

2007