Christopher M Eccles

US Patent:

6574758, Jun 3, 2003

Filed:

Mar 10, 2000

Appl. No.:

09/522629

Inventors:

Christopher M. Eccles - San Francisco CA

Assignee:

Cisco Technology, Inc. - San Jose CA

International Classification:

G06F 1100

US Classification:

714712, 714715

Abstract:

A bus coupled between two circuits (which may be, for example, each implemented as a single chip) is tested by transmitting from a first circuit a predetermined signal on the bus, and recognizing in the second circuit receipt of the predetermined signal. The predetermined signal indicates the beginning of a sequence of test signals that are transmitted therebetween. When any test signal in the sequence is not received correctly, an error signal is generated to specifically identify the test signal that failed, thereby to identify a faulty line in the bus. In one implementation, test signals in the sequence differ each from the other in just the location of a predetermined pattern of bits. For example, a bit pattern 1010 may be located in the beginning, middle or end of three signals of such a sequence. Therefore, in one embodiment, logic in each circuit simply shifts the bits of the predetermined pattern through different positions to obtain the first and second test signals, and such a sequence is called a âwalking pattern. â.

US Patent:

7934198, Apr 26, 2011

Filed:

Oct 18, 2004

Appl. No.:

10/968460

Inventors:

Frederick R. Gruner - Palo Alto CA, US
Gaurav Singh - Santa Clara CA, US
Elango Ganesan - Palo Alto CA, US
Samir C. Vora - Milpitas CA, US
Christopher M. Eccles - San Francisco CA, US
Brian Hang Wai Yang - Monterey Park CA, US

Assignee:

NetLogic Microsystems, Inc. - Santa Clara CA

International Classification:

G06F 9/44
H04L 12/28

US Classification:

717121, 717104, 370351

Abstract:

A prefix matching apparatus for directing information to a destination port includes a memory configured to store a piece of data including an address and a plurality of levels each including a plurality of memory locations, the levels each representing a unique address space. A controller is coupled to the memory and to the plurality of levels, and is configured to read the data address and to direct the data to the next level associated with a unique address space associated with the data address. In one embodiment, the controller is configured to match the data address prefix to a plurality of addresses associated with the unique address spaces. Advantages of the invention include fast switch decisions and low switch latency.