Christopher J Gonzalez

US Patent:

7490308, Feb 10, 2009

Filed:

Mar 31, 2006

Appl. No.:

11/278162

Inventors:

Christopher J. Gonzalez - Elmsford NY, US
Michael S. Gray - Fairfax VT, US
Matthew T. Guzowski - Essex Junction VT, US
Jason D. Hibbeler - Williston VT, US
Stephen I. Runyon - Pflugerville TX, US
Xiaoyun K. Wu - Hopewell Junction NY, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 17/50

US Classification:

716 10, 716 2

Abstract:

A method of modifying a VLSI layout for performance optimization includes defining a revised set of ground rules for a plurality of original device shapes to be modified and flattening the plurality of original device shapes to a prime cell. A layout optimization operation is performed on the flattened device shapes, based on the revised set of ground rules, so as to create a plurality of revised device shapes. An overlay cell is then created from a difference between the revised device shapes and the original device shapes.