Christopher B Gonzalez

US Patent:

7836418, Nov 16, 2010

Filed:

Mar 24, 2008

Appl. No.:

12/053923

Inventors:

William A. Binder - Morrisville NC, US
Christopher J. Gonzalez - Shelburne VT, US
Paul D. Kartschoke - Williston VT, US
Sherwin C. Murphy, Jr. - Cary NC, US

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 9/45
G06F 17/50

US Classification:

716 6, 716 4, 716 5, 703 19

Abstract:

The invention generally relates to integrated circuit design, and more particularly to systems and methods for providing power optimization in a hierarchical netlist. A method includes generating a hierarchical netlist of the design, wherein the design includes a plurality of macros. The method also includes determining the timing slack of each path of the design. For each pin of each one of the plurality of macros, the method includes: determining the worst timing path; determining the slack value of the worst timing path; determining the subset of macros of the plurality of macros associated with the worst timing path; determining an apportionment parameter for each one of the subset of macros; determining a distribution of the slack amongst the subset of macros based upon the respective apportionment parameters; and adjusting timing assertions for each one of the subset of macros based upon the distribution of the slack.