Christopher A Greer

US Patent:

7774562, Aug 10, 2010

Filed:

Sep 17, 2004

Appl. No.:

10/944524

Inventors:

Richard W. Adkisson - Dallas TX, US
Christopher Greer - Allen TX, US

Assignee:

Hewlett-Packard Development Company, L.P. - Houston TX

International Classification:

G06F 13/36

US Classification:

711156, 711144, 711148, 711153

Abstract:

A method of operating a central cache controller (“CCC”) in a first cell of a multiprocessor system comprising multiple cells each including globally shared memory (“GSM”), wherein the first cell is disposed in a first partition and the CCC is connected to a plurality of CPUs of the first cell. In one embodiment, the method comprises, responsive to a new transaction request from one of the CPUs, logging the transaction in a transaction table; determining whether an identity marker in a timeout map corresponding to a cell to which the transaction was issued is set; and, responsive to the corresponding identity marker in the timeout map being set, immediately returning a special error to the one of the CPUs that requested the transaction.

US Patent:

20040225820, Nov 11, 2004

Filed:

May 9, 2003

Appl. No.:

10/434657

Inventors:

Richard Adkisson - Dallas TX, US
Christopher Greer - Allen TX, US

International Classification:

G06F013/36

US Classification:

710/306000

Abstract:

Systems and methods generate transaction identifiers. A plurality of available transaction identifiers are generated for use in identifying future transactions from a first bus. A new transaction identifier is generated upon receipt of each received transaction from the first bus. One of the available transaction identifiers is assigned to each received transaction prior to generation of the new transaction identifier so that the received transaction communicated on a second bus is identified by the one transaction identifier.

US Patent:

20060023819, Feb 2, 2006

Filed:

Jul 29, 2004

Appl. No.:

10/901762

Inventors:

Richard Adkisson - Dallas TX, US
Gary Gostin - Plano TX, US
Christopher Greer - Allen TX, US

International Classification:

H04L 7/00

US Classification:

375354000

Abstract:

A clock synchronizer for effectuating data transfer between first and second clock domains by utilizing first and second synchronizer controllers. The first synchronizer controller circuit operates in the first clock domain which has N first clock cycles and the second synchronizer controller circuit operates in the second clock domain which has M second clock cycles, wherein N/M≧1. Inversion circuitry inverts a first clock signal associated with the first clock domain to generate an inverted first clock signal which is used in effectuating a SYNC pulse during coincident edges of the inverted first clock signal and a second clock signal associated with the second clock domain.