Christopher V Hughes

US Patent:

20120136918, May 31, 2012

Filed:

Nov 29, 2010

Appl. No.:

12/955472

Inventors:

Christopher Hughes - New York NY, US
Nick Thuesen - Brooklyn NY, US

International Classification:

G06F 15/16

US Classification:

709203, 709201

Abstract:

Methods and apparatus for aggregating and distributing information. A user may interact with embodiments of the present invention to access information relating to organizations/projects and issues they are interested in. For example, users may access a web portal which includes information from a wide variety of sources relating to the user's interests in certain organizations/projects and issues.

US Patent:

20220206743, Jun 30, 2022

Filed:

Dec 26, 2020

Appl. No.:

17/134358

Inventors:

- Santa Clara CA, US
Naveen Mellempudi - Bangalore, IN
Robert Valentine - Kiryat Tivon, IL
Mark Charney - Lexington MA, US
Christopher Hughes - Santa Clara CA, US
Evangelos Georganas - San Mateo CA, US
Zeev Sperber - Zichron Yackov, IL
Amit Gradstein - Binyamina, IL
Simon Rubanovich - Haifa, IL

International Classification:

G06F 5/00

Abstract:

Techniques for converting FP16 to BF8 using bias are described. An exemplary embodiment utilizes decoder circuitry to decode a single instruction, the single instruction to include one or more fields to identify a first source operand, one or more fields to identify a second source operand, one or more fields to identify a source/destination operand, and one or more fields for an opcode, wherein the opcode is to indicate that execution circuitry is to convert packed half-precision data from the identified first and second sources to packed bfloat8 data using bias terms from the identified source/destination operand and store the packed bfloat8 data into corresponding data element positions of the identified source/destination operand; and execution circuitry to execute the decoded instruction according to the opcode to convert packed half-precision data from the identified first and second sources to packed bfloat8 data using bias terms from the identified source/destination operand and store the packed bfloat8 data into corresponding data element positions of the identified source/destination operand.

US Patent:

20220206805, Jun 30, 2022

Filed:

Dec 26, 2020

Appl. No.:

17/134353

Inventors:

- Santa Clara CA, US
Naveen Mellempudi - Bangalore, IN
Robert Valentine - Kiryat Tivon, IL
Mark Charney - Lexington MA, US
Christopher Hughes - Santa Clara CA, US
Evangelos Georganas - San Mateo CA, US
Zeev Sperber - Zichron Yackov, IL
Amit Gradstein - Binyamina, IL
Simon Rubanovich - Haifa, IL

International Classification:

G06F 9/30
G06F 7/499
H03M 7/24

Abstract:

Techniques for converting FP16 data elements to BF8 data elements using a single instruction are described. An exemplary apparatus includes decoder circuitry to decode a single instruction, the single instruction to include a one or more fields to identify a source operand, one or more fields to identify a destination operand, and one or more fields for an opcode, the opcode to indicate that execution circuitry is to convert packed half-precision floating-point data from the identified source to packed bfloat8 data and store the packed bfloat8 data into corresponding data element positions of the identified destination operand; and execution circuitry to execute the decoded instruction according to the opcode to convert packed half-precision floating-point data from the identified source to packed bfloat8 data and store the packed bfloat8 data into corresponding data element positions.

US Patent:

20220206945, Jun 30, 2022

Filed:

Dec 25, 2020

Appl. No.:

17/134254

Inventors:

- Santa Clara CA, US
Samantika S. Sury - Westford MA, US
Christopher J. Hughes - Santa Clara CA, US
Lingxiang Xiang - Santa Clara CA, US
Rahul Agrawal - Cupertino CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 12/0811
G06F 12/0817
G06F 12/0862
G06F 12/084

Abstract:

Disclosed embodiments relate to atomic memory operations. In one example, an apparatus includes multiple processor cores, a cache hierarchy, a local execution unit, and a remote execution unit, and an adaptive remote atomic operation unit. The cache hierarchy includes a local cache at a first level and a shared cache at a second level. The local execution unit is to perform an atomic operation at the first level if the local cache is a storing a cache line including data for the atomic operation. The remote execution unit is to perform the atomic operation at the second level. The adaptive remote atomic operation unit is to determine whether to perform the first atomic operation at the first level or at the second level and whether to copy the cache line from the shared cache to the local cache.

US Patent:

20230072105, Mar 9, 2023

Filed:

Aug 31, 2021

Appl. No.:

17/463410

Inventors:

- Santa Clara CA, US
Menachem ADELMAN - Haifa, IL
Robert VALENTINE - Kiryat Tivon, IL
Zeev SPERBER - Zikhron Yaakov, IL
Amit GRADSTEIN - Binyamina, IL
Mark CHARNEY - Lexington MA, US
Evangelos GEORGANAS - San Mateo CA, US
Dhiraj KALAMKAR - Bangalore, IN
Christopher HUGHES - Santa Clara CA, US
Cristina ANDERSON - Hillsboro OR, US

International Classification:

G06F 9/30

Abstract:

Techniques for comparing BF16 data elements are described. An exemplary BF16 comparison instruction includes fields for an opcode, an identification of a location of a first packed data source operand, and an identification of a location of a second packed data source operand, wherein the opcode is to indicate that execution circuitry is to perform, for a particular data element position of the packed data source operands, a comparison of a data element at that position, and update a flags register based on the comparison.

US Patent:

20230067810, Mar 2, 2023

Filed:

Aug 31, 2021

Appl. No.:

17/463405

Inventors:

- Santa Clara CA, US
Menachem ADELMAN - Haifa, IL
Robert VALENTINE - Kiryat Tivon, IL
Zeev SPERBER - Zikhron Yaakov, IL
Amit GRADSTEIN - Binyamina, IL
Mark CHARNEY - Lexington MA, US
Evangelos GEORGANAS - San Mateo CA, US
Dhiraj KALAMKAR - Bangalore, IN
Christopher HUGHES - Santa Clara CA, US
Cristina ANDERSON - Hillsboro OR, US

International Classification:

G06F 9/30
G06F 7/544

Abstract:

Techniques for performing BF16 FMA in response to an instruction are described. In some examples, an instruction has fields for an opcode, an identification of location of a packed data source/destination operand (a first source), an identification of a location of a second packed data source operand, an identification of a location of a third packed data source operand, and an identification of location of a packed data source/destination operand, wherein the opcode is to indicate operand ordering and that execution circuitry is to, per data element position, perform a BF16 value fused multiply-accumulate operation using the first, second, and third source operands and store a result in a corresponding data element position of the source/destination operand

US Patent:

20230069000, Mar 2, 2023

Filed:

Aug 31, 2021

Appl. No.:

17/463398

Inventors:

- Santa Clara CA, US
Menachem ADELMAN - Haifa, IL
Robert VALENTINE - Kiryat Tivon, IL
Zeev SPERBER - Zikhron Yaakov, IL
Amit GRADSTEIN - Binyamina, IL
Mark CHARNEY - Lexington MA, US
Evangelos GEORGANAS - San Mateo CA, US
Dhiraj KALAMKAR - Bangalore, IN
Christopher HUGHES - Santa Clara CA, US
Cristina ANDERSON - Hillsboro OR, US

International Classification:

G06F 9/30

Abstract:

Techniques for performing arithmetic operations on BF16 values are described. An exemplary instruction includes fields for an opcode, an identification of a location of a first packed data source operand, an identification of a location of a second packed data source operand, and an identification of location of a packed data destination operand, wherein the opcode is to indicate an arithmetic operation execution circuitry is to perform, for each data element position of the identified packed data source operands, the arithmetic operation on BF16 data elements in that data element position in BF16 format and store a result of each arithmetic operation into a corresponding data element position of the identified packed data destination operand.

US Patent:

20210405974, Dec 30, 2021

Filed:

Jun 27, 2020

Appl. No.:

16/914318

Inventors:

- Santa Clara CA, US
Robert Valentine - Kiryat Tivon, IL
Barukh Ziv - Haifa, IL
Amit Gradstein - Binyamina, IL
Simon Rubanovich - Haifa, IL
Zeev Sperber - Zichron Yackov, IL
Mark J. Charney - Lexington MA, US
Christopher J. Hughes - Santa Clara CA, US
Alexander F. Heinecke - San Jose CA, US
Evangelos Georganas - San Mateo CA, US
Binh Pham - Burlingame CA, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 7/78
G06F 17/16
G06F 9/30

Abstract:

Embodiments for a matrix transpose and multiply operation are disclosed. In an embodiment, a processor includes a decoder and execution circuitry. The decoder is to decode an instruction having a format including an opcode field to specify an opcode, a first destination operand field to specify a destination matrix location, a first source operand field to specify a first source matrix location, and a second source operand field to specify a second source matrix location. The execution circuitry is to, in response to the decoded instruction, transpose the first source matrix to generate a transposed first source matrix, perform a matrix multiplication using the transposed first source matrix and the second source matrix to generate a result, and store the result in a destination matrix location.