Christopher James Jacobs

US Patent:

8006114, Aug 23, 2011

Filed:

Jun 14, 2007

Appl. No.:

11/818449

Inventors:

Andreas D. Olofsson - Lexington MA, US
Christopher Jacobs - Bedford NH, US
Paul Kettle - Boston MA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G06F 1/06

US Classification:

713500, 714728, 714738, 713502

Abstract:

An apparatus for generating a digital signal pattern may comprises a memory, a program sequencer, first and second circuits, and an event execution unit. The memory may have stored therein a plurality of instructions that, when executed, cause a digital signal pattern to be generated on a plurality of nodes. The program sequencer may be configured to control a sequence in which the plurality of instructions are retrieved from the memory and executed. The first circuit may sequentially step through a plurality of different output states in response to a clock signal. The second circuit may identify an output event when an output state of the first circuit corresponds to an output state identified by retrieved instructions of a particular type. The event execution unit may control states of signals on the plurality of nodes in a manner specified by the retrieved instructions of the particular type in response to the second circuit identifying an output event.

US Patent:

20080222444, Sep 11, 2008

Filed:

Dec 3, 2007

Appl. No.:

11/998994

Inventors:

Andreas D. Olofsson - Lexington MA, US
Christopher Jacobs - Bedford NH, US
Paul Kettle - Boston MA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G06F 9/30
G06F 1/04

US Classification:

713502, 712220, 712E09016

Abstract:

A method for generating a digital signal pattern at M outputs involves retrieving an instruction from memory comprising a first set of bits identifying a first group of N outputs that includes fewer than all of the M outputs, and a second set of N bits each corresponding to a respective output included in the identified first group of N outputs. For each of the M outputs that is included in the identified first group of N outputs, the signal at the output is toggled if the one of the N bits corresponding to that output is in a first state and is kept in the same state if the one of the N bits corresponding to that output is in a second state. For each of the M outputs that is not included in the identified first group of N outputs, the signal at that output is kept in the same state.