Christopher A Kenyon

US Patent:

6864144, Mar 8, 2005

Filed:

May 30, 2002

Appl. No.:

10/158980

Inventors:

Christopher Kenyon - Portland OR, US
Michael R. Fahy - Portland OR, US
Gerard T. Zietz - Banks OR, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L021/336

US Classification:

438302, 438369, 438373, 438506, 438546

Abstract:

A resist material used to mask an underlying layer during an etch process is subjected to ion implantation to harden the resist material against damage from the etch process. In a particular embodiment, the resist material is compatible with exposure to 193 nm radiation for patterning the resist material.

US Patent:

20210249411, Aug 12, 2021

Filed:

Apr 27, 2021

Appl. No.:

17/242021

Inventors:

- Santa Clara CA, US
Biswajeet GUHA - Hillsboro OR, US
Tahir GHANI - Portland OR, US
Christopher N. KENYON - Portland OR, US
Leonard P. GULER - Hillsboro OR, US

International Classification:

H01L 27/092
H01L 21/8238
H01L 29/78
H01L 29/66
H01L 21/768
H01L 23/535

Abstract:

Self-aligned gate edge trigate and finFET devices and methods of fabricating self-aligned gate edge trigate and finFET devices are described. In an example, a semiconductor structure includes a plurality of semiconductor fins disposed above a substrate and protruding through an uppermost surface of a trench isolation region. A gate structure is disposed over the plurality of semiconductor fins. The gate structure defines a channel region in each of the plurality of semiconductor fins. Source and drain regions are on opposing ends of the channel regions of each of the plurality of semiconductor fins, at opposing sides of the gate structure. The semiconductor structure also includes a plurality of gate edge isolation structures. Individual ones of the plurality of gate edge isolation structures alternate with individual ones of the plurality of semiconductor fins.

US Patent:

20200411661, Dec 31, 2020

Filed:

Jun 27, 2019

Appl. No.:

16/454408

Inventors:

- Santa Clara CA, US
Vivek THIRTHA - Portland OR, US
Shu ZHOU - Portland OR, US
Nitesh KUMAR - Beaverton OR, US
Biswajeet GUHA - Hillsboro OR, US
William HSU - Hillsboro OR, US
Dax CRUM - Beaverton OR, US
Oleg GOLONZKA - Beaverton OR, US
Tahir GHANI - Portland OR, US
Christopher KENYON - Portland OR, US

International Classification:

H01L 29/66
H01L 29/06
H01L 21/3105

Abstract:

An integrated circuit structure comprises a semiconductor fin protruding through a trench isolation region above a substrate. A gate structure is over the semiconductor fin. A plurality of vertically stacked nanowires is through the gate structure, wherein the plurality of vertically stacked nanowires includes a top nanowire adjacent to a top of the gate structure, and a bottom nanowire adjacent to a top of the semiconductor fin. A dielectric material covers only a portion of the plurality of vertically stacked nanowires outside the gate structure, such that one or more one of the plurality of vertically stacked nanowires starting with the top nanowire is exposed from the dielectric material. Source and drain regions are on opposite sides of the gate structure connected to the exposed ones of the plurality of vertically stacked nanowires.

US Patent:

20200209734, Jul 2, 2020

Filed:

Nov 28, 2017

Appl. No.:

16/647418

Inventors:

- Santa Clara CA, US
Christopher N. KENYON - Portland OR, US
Sven HENRICHS - San Jose CA, US

International Classification:

G03F 1/36

Abstract:

A mask process development having consistent mask targeting is described. A method includes receiving an integrated (IC) design. A test mask is generated that converts the IC design into one or more physical layouts. A set of one or more sub-resolution assist features (SRAFs) is inserted into the test mask. The set of SRAFs is inserted into one or more other masks, which are derived from the test mask for mask targeting, such that the test mask and the one or more other masks include a same set of the one or more SRAF.

US Patent:

20190304971, Oct 3, 2019

Filed:

Mar 30, 2018

Appl. No.:

15/941647

Inventors:

- Santa Clara CA, US
Sridhar GOVINDARAJU - Portland OR, US
Mark LIU - West Linn OR, US
Szuya S. LIAO - Portland OR, US
Chia-Hong JAN - Portland OR, US
Nick LINDERT - Portland OR, US
Christopher KENYON - Portland OR, US
Sairam SUBRAMANIAN - Portland OR, US

International Classification:

H01L 27/088
H01L 23/528
H01L 29/06

Abstract:

Unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, and methods of fabricating unidirectional self-aligned gate endcap (SAGE) architectures with gate-orthogonal walls, are described. In an example, integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin has a cut along a length of the second semiconductor fin. A gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. The gate endcap isolation structure has a substantially uniform width along the lengths of the first and second semiconductor fins.

US Patent:

20190305111, Oct 3, 2019

Filed:

Apr 2, 2018

Appl. No.:

15/943552

Inventors:

- Santa Clara CA, US
Christopher KENYON - Portland OR, US
Sridhar GOVINDARAJU - Portland OR, US
Chia-Hong JAN - Portland OR, US
Mark LIU - West Linn, UY
Szuya S. LIAO - Portland OR, US
Walid M. HAFEZ - Portland OR, US

International Classification:

H01L 29/66
H01L 21/762
H01L 21/768
H01L 29/06
H01L 21/8238
H01L 27/092

Abstract:

Self-aligned gate endcap (SAGE) architectures having gate endcap plugs or contact endcap plugs, or both gate endcap plugs and contact endcap plugs, and methods of fabricating SAGE architectures having such endcap plugs, are described. In an example, a first gate structure is over a first of a plurality of semiconductor fins. A second gate structure is over a second of the plurality of semiconductor fins. A first gate endcap isolation structure is laterally between and in contact with the first gate structure and the second gate structure and has an uppermost surface co-planar with an uppermost surface of the first gate structure and the second gate structure. A second gate endcap isolation structure is laterally between and in contact with first and second lateral portions of the first gate structure and has an uppermost surface below an uppermost surface of the first gate structure.

US Patent:

20190305112, Oct 3, 2019

Filed:

Apr 2, 2018

Appl. No.:

15/943556

Inventors:

- Santa Clara CA, US
Walid M. HAFEZ - Portland OR, US
Sridhar GOVINDARAJU - Portland OR, US
Mark LIU - West Linn OR, US
Szuya S. LIAO - Portland OR, US
Chia-Hong JAN - Portland OR, US
Nick LINDERT - Portland OR, US
Christopher KENYON - Portland OR, US

International Classification:

H01L 29/66
H01L 29/06
H01L 21/768
H01L 21/8234
H01L 21/762
H01L 27/088

Abstract:

Dual self-aligned gate endcap (SAGE) architectures, and methods of fabricating dual self-aligned gate endcap (SAGE) architectures, are described. In an example, an integrated circuit structure includes a first semiconductor fin having a cut along a length of the first semiconductor fin. A second semiconductor fin is parallel with the first semiconductor fin. A first gate endcap isolation structure is between the first semiconductor fin and the second semiconductor fin. A second gate endcap isolation structure is in a location of the cut along the length of the first semiconductor fin.