Christopher Andrew Lamb

US Patent:

8180998, May 15, 2012

Filed:

Sep 10, 2008

Appl. No.:

12/208231

Inventors:

Monier Maher - St. Louis MO, US
Christopher Lamb - San Jose CA, US
Sanjay J. Patel - Urbana IL, US
Peter Hsu - San Francisco CA, US

Assignee:

NVIDIA Corporation - Santa Clara CA

International Classification:

G06F 15/16

US Classification:

712 20, 712 21, 712 22

Abstract:

A system for performing data-parallel operations and task-parallel operations. A first switch fabric node (SFN) includes first and second lane processing engines (LPEs). The first LPE includes a first set of lane processing units (LPUs) configured to perform data-parallel operations, where each LPU performs a set of operations, and each LPU uses a different set of data for the set of operations, and each LPU within the first set of LPUs uses a different set of data for the set of operations. The second LPE includes a second set of LPUs configured to perform task-parallel operations, where each LPU performs a different set of operations. A processing control engine (PCE) is configured to distribute instructions and data to the first LPE and the second LPE. Advantageously, data parallel operations and task parallel operations are able to be performed on the same processor simultaneously.

US Patent:

20130117760, May 9, 2013

Filed:

Nov 8, 2011

Appl. No.:

13/291476

Inventors:

Philip Alexander Cuadra - Mountain View CA, US
Christopher Lamb - San Jose CA, US
Lacky V. Shah - Los Altos Hills CA, US

International Classification:

G06F 9/46

US Classification:

718108

Abstract:

One embodiment of the present invention sets forth a technique for instruction level execution preemption. Preempting at the instruction level does not require any draining of the processing pipeline. No new instructions are issued and the context state is unloaded from the processing pipeline. Any in-flight instructions that follow the preemption command in the processing pipeline are captured and stored in a processing task buffer to be reissued when the preempted program is resumed. The processing task buffer is designated as a high priority task to ensure the preempted instructions are reissued before any new instructions for the preempted context when execution of the preempted context is restored.

US Patent:

20130124838, May 16, 2013

Filed:

Nov 10, 2011

Appl. No.:

13/294045

Inventors:

Lacky V. SHAH - Los Altos Hills CA, US
Gregory Scott Palmer - Cedar Park TX, US
Gernot Schaufler - Mountain View CA, US
Samuel H. Duncan - Arlington MA, US
Philip Browning Johnson - Campbell CA, US
Shirish Gadre - Fremont CA, US
Robert Ohannessian - Austin TX, US
Nicholas Wang - Saratoga CA, US
Christopher Lamb - San Jose CA, US
Philip Alexander Cuadra - Mountain View CA, US
Timothy John Purcell - Provo UT, US

International Classification:

G06F 9/38

US Classification:

712234, 712E09062

Abstract:

One embodiment of the present invention sets forth a technique instruction level and compute thread array granularity execution preemption. Preempting at the instruction level does not require any draining of the processing pipeline. No new instructions are issued and the context state is unloaded from the processing pipeline. When preemption is performed at a compute thread array boundary, the amount of context state to be stored is reduced because execution units within the processing pipeline complete execution of in-flight instructions and become idle. If, the amount of time needed to complete execution of the in-flight instructions exceeds a threshold, then the preemption may dynamically change to be performed at the instruction level instead of at compute thread array granularity.

US Patent:

20130298133, Nov 7, 2013

Filed:

May 2, 2012

Appl. No.:

13/462649

Inventors:

Stephen JONES - San Francisco CA, US
Philip Alexander Cuadra - San Francisco CA, US
Daniel Elliot Wexler - Soda Springs CA, US
Ignacio Llamas - Sunnyvale CA, US
Lacky V. Shah - Los Altos Hills CA, US
Christopher Lamb - San Jose CA, US

International Classification:

G06F 9/50

US Classification:

718104

Abstract:

One embodiment of the present invention sets forth a technique for performing nested kernel execution within a parallel processing subsystem. The technique involves enabling a parent thread to launch a nested child grid on the parallel processing subsystem, and enabling the parent thread to perform a thread synchronization barrier on the child grid for proper execution semantics between the parent thread and the child grid. This technique advantageously enables the parallel processing subsystem to perform a richer set of programming constructs, such as conditionally executed and nested operations and externally defined library functions without the additional complexity of CPU involvement.

US Patent:

61855200, Feb 6, 2001

Filed:

May 22, 1998

Appl. No.:

9/083909

Inventors:

David Robert Brown - San Jose CA
Christopher Hume Lamb - Weston MA

Assignee:

3Com Corporation - Santa Clara CA

International Classification:

G06F 9455

US Classification:

703 25

Abstract:

In a computer system having a plurality of peripheral devices, a data transfer system for implementing transparent direct communication between the devices and the computer system. The system of the present invention includes a switch having a plurality of ports. Each of the plurality of ports is adapted to couple to a respective one of a plurality of devices. Each of the plurality of ports is further adapted to accept data from its respective device and transmit data to its respective device in a bi-directional manner. The switch communicatively couples a first pair of the plurality of ports to enable communication between their respective devices and communicatively couples a second pair of the plurality of ports to enable communication between their respective devices such that communication between the first pair of ports and communication between the second pair of ports occurs simultaneously and independently, thereby implementing efficient switched data transfers between the respective devices and greatly increasing the total data transfer bandwidth of the computer system.

US Patent:

20210349763, Nov 11, 2021

Filed:

Feb 5, 2021

Appl. No.:

17/169283

Inventors:

- Santa Clara CA, US
Philip Alexander Cuadra - San Francisco CA, US
Daniel Elliot Wexler - Soda Springs CA, US
Ignacio Llamas - Sunnyvale CA, US
Lacky V. Shah - Los Altos Hills CA, US
Christopher Lamb - San Jose CA, US

International Classification:

G06F 9/50
G06T 1/20
G06F 9/52

Abstract:

One embodiment of the present invention sets forth a technique for performing nested kernel execution within a parallel processing subsystem. The technique involves enabling a parent thread to launch a nested child grid on the parallel processing subsystem, and enabling the parent thread to perform a thread synchronization barrier on the child grid for proper execution semantics between the parent thread and the child grid. This technique advantageously enables the parallel processing subsystem to perform a richer set of programming constructs, such as conditionally executed and nested operations and externally defined library functions without the additional complexity of CPU involvement.

US Patent:

20170249151, Aug 31, 2017

Filed:

May 12, 2017

Appl. No.:

15/594515

Inventors:

- Santa Clara CA, US
Christopher Lamb - San Jose CA, US
Lacky V. Shah - Los Altos Hills CA, US

International Classification:

G06F 9/38

Abstract:

One embodiment of the present invention sets forth a technique for instruction level execution preemption. Preempting at the instruction level does not require any draining of the processing pipeline. No new instructions are issued and the context state is unloaded from the processing pipeline. Any in-flight instructions that follow the preemption command in the processing pipeline are captured and stored in a processing task buffer to be reissued when the preempted program is resumed. The processing task buffer is designated as a high priority task to ensure the preempted instructions are reissued before any new instructions for the preempted context when execution of the preempted context is restored.

US Patent:

20170249152, Aug 31, 2017

Filed:

May 12, 2017

Appl. No.:

15/594516

Inventors:

- Santa Clara CA, US
Christopher Lamb - San Jose CA, US
Lacky V. Shah - Los Altos Hills CA, US

International Classification:

G06F 9/38

Abstract:

One embodiment of the present invention sets forth a technique for instruction level execution preemption. Preempting at the instruction level does not require any draining of the processing pipeline. No new instructions are issued and the context state is unloaded from the processing pipeline. Any in-flight instructions that follow the preemption command in the processing pipeline are captured and stored in a processing task buffer to be reissued when the preempted program is resumed. The processing task buffer is designated as a high priority task to ensure the preempted instructions are reissued before any new instructions for the preempted context when execution of the preempted context is restored.