Christopher D Lane

US Patent:

6335634, Jan 1, 2002

Filed:

May 22, 2000

Appl. No.:

09/577297

Inventors:

Srinivas T. Reddy - Fremont CA 94539
Ketan Zaveri - San Jose CA 95129
Christopher F. Lane - Campbell CA 95008
Andy L. Lee - San Jose CA 95131
Cameron R. McClintock - Mountain View CA 94043
Bruce B. Pedersen - San Jose CA 95136
Manuel Mejia - San Jose CA 95116
Richard G. Cliff - Milpitas CA 95116

International Classification:

G06F 738

US Classification:

326 41, 326 40, 326 39, 326 38

Abstract:

Programmable interconnection group arrangements for selectively interconnecting logic on a programmable logic device are provided. Interconnection groups may be programmed to route signals between the various conductors on the device, and to route signals from various logic regions on the device to the various conductors. The interconnection groups provide routing flexibility and efficiency without using excessive amounts of interconnection resources.

US Patent:

6356110, Mar 12, 2002

Filed:

Sep 29, 2000

Appl. No.:

09/675727

Inventors:

Srinivas T. Reddy - Fremont CA
Brian D. Johnson - Sunnyvale CA
Christopher F. Lane - San Jose CA
Ketan H. Zaveri - San Jose CA

Assignee:

Altera Corporation San Jose CA

International Classification:

H01L 2501

US Classification:

326 41, 326 38, 326 39

Abstract:

A logic array block (LAB) that is programmably selectively configurable for use as a multifunction memory array is provided. The LAB is configurable for operation in at least two modes: in a first mode, each logic element within the LAB is individually configurable to perform logic functions; in a second mode, the logic elements are collectively usable as a multifunction memory array. The multifunction memory array may be addressed on a LAB-wide basis with separate read and write addresses, such that it may be configured to implement a variety of memory schemes, including first-in-first-out (FIFO) memory and random access memory (RAM).

US Patent:

6392954, May 21, 2002

Filed:

Dec 21, 2000

Appl. No.:

09/747191

Inventors:

Srinivas T. Reddy - Fremont CA
Christopher F. Lane - Campbell CA
Manuel Mejia - San Jose CA
Richard G. Cliff - Milpitas CA
Kerry Veenstra - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

G11C 800

US Classification:

36523005, 36518902, 36523002

Abstract:

A dual-port programmable logic device memory array is provided. Selectable-size data words may be written to and read from the array concurrently. Data is written into the array using write column decoder and data selection logic. The size of the data words handled by the write column decoder and data selection logic is controlled by mode select signals. Data is read from the array using read column decoder and data selection logic. The size of the data words handled by the read column decoder and data selection logic is also controlled by mode select signals. The write column decoder and data selection logic may be used to write data into the memory array at one selected location at the same time that the read column decoder and data selection logic is used to read data from the array at another selected location. A write row address decoder and a read row address decoder are used to independently address individual rows of memory cells in the memory array during writing and reading, respectively.

US Patent:

6417694, Jul 9, 2002

Filed:

Sep 19, 2001

Appl. No.:

09/956748

Inventors:

Srinivas T. Reddy - Fremont CA
Richard G. Cliff - Milpitas CA
Christopher F. Lane - Campbell CA
Ketan H. Zaveri - San Jose CA
Manuel M. Mejia - San Jose CA
David Jefferson - San Jose CA
Bruce B. Pedersen - San Jose CA
Andy L. Lee - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19177

US Classification:

326 41, 326 39

Abstract:

A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e. g.

US Patent:

6577160, Jun 10, 2003

Filed:

Jun 10, 2002

Appl. No.:

10/170026

Inventors:

Srinivas T. Reddy - Fremont CA
Richard G. Cliff - Milpitas CA
Christopher F. Lane - Campbell CA
Ketan H. Zaveri - San Jose CA
Manuel M. Mejia - San Jose CA
David Jefferson - San Jose CA
Bruce B. Pedersen - San Jose CA
Andy L. Lee - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19177

US Classification:

326 41, 326 39

Abstract:

A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region. Local conductors are associated with each region. Shared driver circuits may be provided (e. g. , for (1) receiving signals from the subregions and the horizontal and/or vertical conductors, and (2) applying selected received signals to the inter-region conductors, the horizontal and vertical conductors, and possibly also the local conductors). The horizontal and/or vertical conductors may be axially segmented and buffering circuitry may be provided for programmably stitching together axial segments to make longer conductors.

US Patent:

6720796, Apr 13, 2004

Filed:

May 6, 2002

Appl. No.:

10/140311

Inventors:

Srinivas Reddy - Fremont CA
David Jefferson - Morgan Hill CA
Christopher F. Lane - San Jose CA
Vikram Santurkar - San Jose CA
Richard Cliff - Los Altos CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19177

US Classification:

326 39, 326 41, 326 40

Abstract:

A programmable logic device (PLD) includes a first memory block and at least a second memory block, where the two memory blocks have different memory sizes.

US Patent:

6798242, Sep 28, 2004

Filed:

Apr 29, 2003

Appl. No.:

10/426991

Inventors:

Srinivas T. Reddy - Fremont CA
Richard G. Cliff - Milpitas CA
Christopher F. Lane - Campbell CA
Ketan H. Zaveri - San Jose CA
Manuel M. Mejia - San Jose CA
David Jefferson - San Jose CA
Bruce B. Pedersen - San Jose CA
Andy L. Lee - San Jose CA

Assignee:

Altera Corporation - San Jose CA

International Classification:

H03K 19177

US Classification:

326 41, 326 39

Abstract:

A programmable logic device has a plurality of super-regions of programmable logic disposed on the device in a two-dimensional array of intersecting rows and columns of super-regions. Horizontal and vertical inter-super-region interconnection conductors are associated with each row and column, respectively. Each super-region includes a plurality of regions of programmable logic, and each region includes a plurality of subregions of programmable logic. Inter-region interconnection conductors are associated with each super-region, principally for bringing signals into the super-region and interconnecting the regions in the super-region. Local conductors are associated with each region, principally for bringing signals into the region. At the super-region level the device may be horizontally and vertically isomorphic, which helps make it possible to produce devices with low aspect ratios of one or nearly one. Shared driver circuits may be provided (e. g.

US Patent:

6895570, May 17, 2005

Filed:

Jan 25, 2002

Appl. No.:

10/057232

Inventors:

David M. Lewis - Toronto, CA
Vaughn Betz - Toronto, CA
Paul Leventis - Toronto, CA
Michael Chan - Scarborough, CA
Cameron R. McClintock - Mountain View CA, US
Andy L. Lee - San Jose CA, US
Christopher F. Lane - San Jose CA, US
Srinivas T. Reddy - Fremont CA, US
Richard Cliff - Los Altos CA, US

Assignee:

Altera Corporation - San Jose CA

International Classification:

G06F017/50

US Classification:

716 16, 716 12

Abstract:

An embodiment of this invention pertains to a wire that interconnects multiple function blocks within a programmable logic device (“PLD”). An electrically optimum physical length is determined for the wire. A wire having the electrically optimum physical length transmits a signal down the wire as fast as possible. Some of the wires used in the PLD have a physical length substantially the same as the electrically optimum physical length or an adjustment of the electrically optimum physical length to account for non-electrical considerations. The physical length, as used herein, is the measured length of the wire. A logical length of the wire, as used herein, is the number of function blocks that the wire spans. Given that the function blocks have a different height and width, the logical length of the wire varies depending on the orientation of the wire. A routing architecture is an array that includes rows and columns of function blocks.