Christopher S Larsen

US Patent:

20130260521, Oct 3, 2013

Filed:

May 24, 2013

Appl. No.:

13/902052

Inventors:

Christopher J. Larsen - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 29/66

US Classification:

438264

Abstract:

A method of forming a memory array includes forming a dielectric over a semiconductor, forming a charge-storage structure over the dielectric, forming an isolation region through the dielectric and the charge-storage structure and extending into the semiconductor, recessing the isolation region to a level below a level of an upper surface of the dielectric and at or above a level of an upper surface of the semiconductor, forming an access line over the charge-storage structure and the recessed isolation region, and forming an air gap over the recessed isolation region so that the air gap passes through the charge-storage structure, so that the air gap extends to and terminates at a bottom surface of the access line, and so that the entire air gap is between the bottom surface of the access line and the upper surface of the semiconductor.

US Patent:

20130264628, Oct 10, 2013

Filed:

Sep 22, 2011

Appl. No.:

13/993444

Inventors:

Randy J. Koval - Boise ID, US
Max F. Hineman - Boise ID, US
Ronald A. Weimer - Boise ID, US
Vinayak K. Shamanna - Boise ID, US
Thomas M. Graettinger - Boise ID, US
William R. Kueber - Boise ID, US
Christopher Larsen - Boise ID, US
Alex J. Schrinsky - Boise ID, US

International Classification:

H01L 21/306
H01L 29/788

US Classification:

257316, 438593

Abstract:

Embodiments of the present disclosure describe techniques and configurations relating to use of an etch process post wordline definition to improve data retention in a flash memory device. In one embodiment, a method includes forming a plurality of wordline structures on a substrate, wherein individual wordline structures of the plurality of wordline structures include a control gate having an electrically conductive material and a cap having an electrically insulative material formed on the control gate, depositing an electrically insulative material to form a liner on a surface of the individual wordline structures, and etching the liner to remove at least a portion of the liner. Other embodiments may be described and/or claimed.

US Patent:

20220367512, Nov 17, 2022

Filed:

Jul 20, 2022

Appl. No.:

17/869732

Inventors:

- Boise ID, US
Prakash Rau Mokhna Rau - Boise ID, US
Arun Kumar Dhayalan - Boise ID, US
Damir Fazil - Boise ID, US
Joel D. Peterson - Boise ID, US
Anilkumar Chandolu - Boise ID, US
George Matamis - Eagle ID, US
Christopher Larsen - Boise ID, US
Rokibul Islam - Meridian ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 27/11582
G11C 5/02
H01L 21/768
G11C 16/04
G11C 5/06

Abstract:

Some embodiments include an integrated assembly having a first deck. The first deck has first memory cell levels alternating with first insulative levels. A second deck is over the first deck. The second deck has second memory cell levels alternating with second insulative levels. A cell-material-pillar passes through the first and second decks. Memory cells are along the first and second memory cell levels and include regions of the cell-material-pillar. An intermediate level is between the first and second decks. The intermediate level includes a buffer region adjacent the cell-material-pillar. The buffer region includes a composition different from the first and second insulative materials, and different from the first and second conductive regions. Some embodiments include methods of forming integrated assemblies.

US Patent:

20220310632, Sep 29, 2022

Filed:

Jun 14, 2022

Appl. No.:

17/806829

Inventors:

- Boise ID, US
Christopher J. Larsen - Boise ID, US
Anilkumar Chandolu - Boise ID, US
Wesley O. Mckinsey - Nampa ID, US
Tom J. John - Boise ID, US
Arun Kumar Dhayalan - Boise ID, US
Prakash Rau Mokhna Rau - Boise ID, US

International Classification:

H01L 27/1157
H01L 27/11578
H01L 27/11524
H01L 27/11556

Abstract:

An electronic device comprising a lower deck and an upper deck adjacent to a source. Each of the lower deck and the upper deck comprise tiers of alternating conductive materials and dielectric materials. Each of the lower deck and the upper deck also comprise an array region and one or more non-array regions. Memory pillars are in the lower deck and the upper deck of the array region and the memory pillars are configured to be operably coupled to the source. Dummy pillars are in the upper deck of the one or more non-array regions and the dummy pillars are configured to be electrically isolated from the source. Another conductive material is in the upper deck and the lower deck of the one or more non-array regions. Additional electronic devices and related systems and methods of forming an electronic device are also disclosed.

US Patent:

20220231031, Jul 21, 2022

Filed:

Jan 20, 2021

Appl. No.:

17/153740

Inventors:

- Boise ID, US
Harsh Narendrakumar Jain - Boise ID, US
Nancy M. Lomeli - Boise ID, US
Christopher J. Larsen - Boise ID, US

International Classification:

H01L 27/1157
H01L 27/11524
H01L 27/11556
H01L 27/11529
H01L 27/11582
H01L 27/11573
H01L 23/00
H01L 23/528
H01L 23/522

Abstract:

A method of forming a microelectronic device includes forming a microelectronic device structure. The microelectronic device structure includes a stack structure having an alternating sequence of conductive structures and insulative structures, an upper stadium structure, a lower stadium structure, and a crest region defined between a first stair step structure of the upper stadium structure and a second stair step structure of the lower stadium structure. The stack structure further includes pillar structures extending through the stack structure and dielectric structures interposed between neighboring pillar structures within the upper stadium structure. The method further includes forming a trench in the crest region of the stack structure between two dielectric structures of the dielectric structures on opposing sides of another dielectric structure and filling the trench with a dielectric material. The trench partially overlaps with the dielectric structures.

US Patent:

20230017241, Jan 19, 2023

Filed:

Sep 19, 2022

Appl. No.:

17/933227

Inventors:

- Boise ID, US
Tom J. John - Boise ID, US
Darwin A. Clampitt - Wilder ID, US
Anilkumar Chandolu - Boise ID, US
Prakash Rau Mokhna Rau - Boise ID, US
Christopher J. Larsen - Boise ID, US
Kye Hyun Baek - Boise ID, US

International Classification:

H01L 27/11582
H01L 21/768

Abstract:

An electronic device comprising lower and upper decks adjacent to a source. The lower and upper decks comprise tiers of alternating conductive materials and dielectric materials. Memory pillars in the lower and upper decks are configured to be operably coupled to the source. The memory pillars comprise contact plugs in the upper deck, cell films in the lower and upper decks, and fill materials in the lower and upper decks. The cell films in the upper deck are adjacent to the contact plugs and the fill materials in the upper deck are adjacent to the contact plugs. Dummy pillars are in a central region of the lower deck and the upper deck. The dummy pillars comprise an oxide material in the upper deck, the oxide material contacting the contact plugs and the fill materials. Additional electronic devices and related systems and methods are also disclosed.

US Patent:

20210327885, Oct 21, 2021

Filed:

Apr 17, 2020

Appl. No.:

16/851638

Inventors:

- Boise ID, US
Christopher J. Larsen - Boise ID, US
Anilkumar Chandolu - Boise ID, US
Wesley O. McKinsey - Nampa ID, US
Tom J. John - Boise ID, US
Arun Kumar Dhayalan - Boise ID, US
Prakash Rau Mokhna Rau - Boise ID, US

International Classification:

H01L 27/1157
H01L 27/11556
H01L 27/11524
H01L 27/11578

Abstract:

An electronic device comprising a lower deck and an upper deck adjacent to a source. Each of the lower deck and the upper deck comprise tiers of alternating conductive materials and dielectric materials. Each of the lower deck and the upper deck also comprise an array region and one or more non-array regions. Memory pillars are in the lower deck and the upper deck of the array region and the memory pillars are configured to be operably coupled to the source. Dummy pillars are in the upper deck of the one or more non-array regions and the dummy pillars are configured to be electrically isolated from the source. Another conductive material is in the upper deck and the lower deck of the one or more non-array regions. Additional electronic devices and related systems and methods of forming an electronic device are also disclosed.

US Patent:

20210265171, Aug 26, 2021

Filed:

May 12, 2021

Appl. No.:

17/318470

Inventors:

- Boise ID, US
Gordon A. Haller - Boise ID, US
Tom J. John - Boise ID, US
Anish A. Khandekar - Boise ID, US
Christopher Larsen - Boise ID, US
Kunal Shrotri - Boise ID, US

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 21/311
H01L 27/11556
H01L 21/02
H01L 27/11582

Abstract:

A method used in forming an array of elevationally-extending strings of memory cells comprises forming a stack comprising vertically-alternating insulative tiers and wordline tiers. The stack comprises an etch-stop tier between a first tier and a second tier of the stack. The etch-stop tier is of different composition from those of the insulative tiers and the wordline tiers. Etching is conducted into the insulative tiers and the wordline tiers that are above the etch-stop tier to the etch-stop tier to form channel openings that have individual bases comprising the etch-stop tier. The etch-stop tier is penetrated through to extend individual of the channel openings there-through. After extending the individual channel openings through the etch-stop tier, etching is conducted into and through the insulative tiers and the wordline tiers that are below the etch-stop tier to extend the individual channel openings deeper into the stack below the etch-stop tier. Transistor channel material is formed in the individual channel openings elevationally along the etch-stop tier and along the insulative tiers and the wordline tiers that are above and below the etch-stop tier. Arrays independent of method are disclosed.