Christopher B Long

US Patent:

20220318181, Oct 6, 2022

Filed:

Jun 22, 2022

Appl. No.:

17/846305

Inventors:

- Broomfield CO, US
Christopher R. Long - Colorado Springs CO, US
Phillip Clark - Boulder CO, US
Sumit Puri - Calabasas CA, US

International Classification:

G06F 13/42
G06F 9/4401

Abstract:

A method of programming a fabric-coupled FPGA device includes instructing a communication fabric to establish a first logical partition segregating a first set of communication switch ports within the communication fabric that includes the management processor and a target device comprising a memory device configured to program a field-programmable gate array (FPGA). The method includes directing configuration data configured to program the FPGA to the target device over the first logical partition. The method includes instructing the communication fabric to remove the first logical partition in the communication fabric, wherein the configuration data remains stored at the target device after removal of the first logical partition. The method includes instructing the communication fabric to establish a second logical partition segregating a second set of communication switch ports within the communication fabric that includes a selected device and the target device that stores the configuration data.

US Patent:

20220283974, Sep 8, 2022

Filed:

May 14, 2021

Appl. No.:

17/320870

Inventors:

- Broomfield CO, US
Christopher R. Long - Colorado Springs CO, US

Assignee:

Liqid Inc. - Broomfield CO

International Classification:

G06F 13/40

Abstract:

Deployment of arrangements of physical computing components coupled over a communication fabric are presented herein. In one example, a method includes coupling into a communication fabric a plurality of communication interfaces provided by a baseboard hosting a plurality data processing devices. The method includes establishing a one-hop latency in the communication fabric between the plurality of data processing devices and peripheral card slots, and establishing a two-hop latency in the communication fabric between the plurality of data processing devices and additional peripheral card slots. The method also includes establishing interconnect pathways between a plurality of communication switches that provide the one-hop latency through one or more cross-connect communication switches that provide the two-hop latency.

US Patent:

20220283976, Sep 8, 2022

Filed:

Nov 11, 2021

Appl. No.:

17/524273

Inventors:

- Broomfield CO, US
Christopher R. Long - Colorado Springs CO, US

International Classification:

G06F 13/40
G06F 1/3234
G06F 1/3215

Abstract:

Designs for enabling safe insertion and removal of computing components from a live motherboard are presented herein. In one example, a method includes maintaining a slot power connection and an auxiliary power connection for a peripheral card slot in a powered-off state, and sensing insertion of a peripheral card into the peripheral card slot and responsively detecting whether the auxiliary power connection is employed by the peripheral card. Based on detecting the auxiliary power connection is employed by the peripheral card, the method further includes applying current limits selected for the peripheral card to the slot power connection and the auxiliary power connection and concurrently enabling the slot power connection and the auxiliary power connection for the peripheral card. Based on detecting the auxiliary power connection is not employed by the peripheral card, the method further includes applying a current limit selected for the peripheral card to the slot power connection and enabling only the slot power connection for the peripheral card.

US Patent:

20220214987, Jul 7, 2022

Filed:

Mar 22, 2022

Appl. No.:

17/701041

Inventors:

- Broomfield CO, US
German Kazakov - Longmont CO, US
Christopher R. Long - Colorado Springs CO, US
Jason Breakstone - Broomfield CO, US

International Classification:

G06F 13/40
G06T 1/20
G06F 13/42
G06F 12/02
G06F 9/50
G06F 13/28

Abstract:

Peer-to-peer arrangements between graphics processing units (GPUs) are provided herein. A method includes establishing synthetic devices representing GPUs in an address domain associated with a host processor, where the GPUs have a different address domain than the host processor. The method also includes forming a peer arrangement between the GPUs such that data transfers between the GPUs in the different address domain can be initiated by the host processor interfacing with the synthetic devices.

US Patent:

20220214989, Jul 7, 2022

Filed:

Mar 23, 2022

Appl. No.:

17/702057

Inventors:

- Broomfield CO, US
Christopher R. Long - Colorado Springs CO, US
Jason Breakstone - Broomfield CO, US

International Classification:

G06F 13/40
G06F 3/06
G06F 9/54

Abstract:

Emulated telemetry interfaces for host processors and management processors coupled over communication fabrics are presented herein. In one example, an apparatus includes a monitoring function executed by a host processor configured to determine telemetry related to operation of at least the host processor. A driver function executed by the host processor is configured to emulate operation of a network interface to an operating system of the host processor for transfer of communications comprising at least the telemetry to a management processor over a communication fabric different than the network interface, where the host processor and the management processor are communicatively coupled to the communication fabric.

US Patent:

20220206687, Jun 30, 2022

Filed:

Jan 13, 2022

Appl. No.:

17/575062

Inventors:

- Broomfield CO, US
Christopher R. Long - Colorado Springs CO, US
Phillip Clark - Boulder CO, US
Sumit Puri - Calabasas CA, US

Assignee:

Liqid Inc. - Broomfield CO

International Classification:

G06F 3/06

Abstract:

Disaggregated computing architectures, platforms, and systems are provided herein. In one example, a method includes instructing a communication fabric to establish a first logical partition in the communication fabric that includes a first processing device and a memory device, and directing transfer of configuration data for storage by the memory device over the first logical partition. After transfer of the configuration data, the method includes instructing the communication fabric to remove the first logical partition in the communication fabric, where the configuration data remains stored by the memory device after removal of the first logical partition. The method also includes instructing the communication fabric to establish a second logical partition in the communication fabric that includes at least a second processing device and the memory device comprising the configuration data, where the second processing device is operated using the configuration data.

US Patent:

20200301863, Sep 24, 2020

Filed:

Jun 5, 2020

Appl. No.:

16/893638

Inventors:

- Broomfield CO, US
Christopher R. Long - Colorado Springs CO, US

Assignee:

Liqid Inc. - Broomfield CO

International Classification:

G06F 13/40
H04L 12/743

Abstract:

Computing architectures, platforms, and systems are provided herein. In one example, a system is provided. The system includes a communication arrangement for peripheral component interconnect express (PCIe) traffic transferred over a communication fabric. The communication arrangement establishes an expanded address that provides a quantity of port identifiers to a host greater than indicated by a quantity of bits in a port field of the PCIe traffic, where the expanded address employs one or more bits of the PCIe traffic other than the port field. The communication arrangement detects a transfer among the PCIe traffic issued by the host having the expanded address corresponding to a destination. Based on the expanded address, the communication arrangement identifies routing information to route the transfer over the communication fabric to the destination.

US Patent:

20200296853, Sep 17, 2020

Filed:

May 18, 2020

Appl. No.:

16/876749

Inventors:

- Broomfield CO, US
Andrew Rudolph Heyd - Longmont CO, US
Brenden Michael Rust - Loveland CO, US
Christopher R. Long - Colorado Springs CO, US
Sumit Puri - Calabasas CA, US

Assignee:

Liqid Inc. - Broomfield CO

International Classification:

H05K 7/14
G06F 1/18

Abstract:

A storage card insertable into a host system is provided that includes a plurality of storage devices connectors. The storage card include slot offset features to offset a circuit board of the storage card from a host system slot alignment. This offset provides for storage device connector placement on both sides of the storage card. The storage card also can include a Peripheral Component Interconnect Express (PCIe) switch circuit configured to communicatively couple the PCIe signaling of the plurality of storage device connectors and PCIe signaling of a host connector of the storage card, where the PCIe switch circuit is configured to receive storage operations over the PCIe signaling of the host connector of the storage card and transfer the storage operations for delivery over the PCIe signaling of selected ones of the plurality of storage device connectors.