Christopher F Lyons

US Patent:

6350559, Feb 26, 2002

Filed:

Sep 17, 1999

Appl. No.:

09/398642

Inventors:

Michael K. Templeton - Atherton CA
Kathleen R. Early - Santa Clara CA
Christopher F. Lyons - Fremont CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G03F 700

US Classification:

430322, 430327, 216 38

Abstract:

In one embodiment, the present invention relates to a method of forming a thin photoresist layer having a low defect density, involving the steps of depositing a photoresist layer having a thickness from greater than about 0. 5 m to about 2 m on a semiconductor substrate; and removing at least a portion of the photoresist layer to provide the thin photoresist layer having the low defect density and a thickness from about 0. 1 m to about 0. 5 m. In another embodiment, the present invention relates to a method of reducing pinhole defects in a thin photoresist layer having a thickness below about 0. 5 m comprising a photoresist material, involving the steps of depositing a layer of the photoresist material having a thickness greater than about 0. 5 m; and etching at least a portion of the photoresist material to provide the thin photoresist layer having the thickness below about 0. 5 m, wherein the thickness of the thin photoresist layer is about 90% or less than the thickness of the layer of the photoresist material.

US Patent:

6358856, Mar 19, 2002

Filed:

Nov 21, 2000

Appl. No.:

09/716215

Inventors:

Christopher F. Lyons - Fremont CA
Ramkumar Subramanian - Sunnyvale CA
Marina V. Plat - San Jose CA
Todd P. Lukanc - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21311

US Classification:

438703, 438713

Abstract:

A method of forming a small contact hole uses a bright field mask to form a small cylinder in a positive resist layer. A negative resist layer is formed around the small cylinder, and then etched or polished back to leave a top portion of the small cylinder exposed above the negative resist layer. The negative resist layer and the small cylinder (positive resist) are flood exposed to light, and then subject to a developer. What remains is a small contact hole located where the small cylinder was previously located.

US Patent:

6380047, Apr 30, 2002

Filed:

Aug 8, 2000

Appl. No.:

09/634990

Inventors:

Basab Bandyopadhyay - Austin TX
Nick Kepler - Saratoga CA
Olov Karlsson - San Jose CA
Larry Wang - San Jose CA
Effiong Ibok - Sunnyvale CA
Christopher F. Lyons - Fremont CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2176

US Classification:

438427, 438424, 438433

Abstract:

An insulated trench isolation structure with large and small trenches of differing widths is formed in a semiconductor substrate with improved planarity using a simplified reverse source/drain planarization mask. Embodiments include forming large trenches and refilling them with an insulating material which also covers the substrate surface, masking the areas above the large trenches, etching to remove substantially all of the insulating material on the substrate surface and polishing to planarize the insulating material above the large trenches. Small trenches and peripheral trenches surrounding the large trenches are then formed, refilled with insulating material, and planarized. Since the large trenches are formed prior to and separately from the small trenches, etching can be carried out after the formation of a relatively simple planarization mask over only the large trenches, and not the small trenches. The use of a planarization mask with relatively few features having a relatively large geometry avoids the need to create and implement a complex and critical mask, thereby reducing manufacturing costs and increasing production throughput. Furthermore, because the large and small trenches are not polished at the same time, overpolishing is avoided, thereby improving planarity and, hence, the accuracy of subsequent photolithographic processing.

US Patent:

6380067, Apr 30, 2002

Filed:

May 31, 2000

Appl. No.:

09/588119

Inventors:

Ramkumar Subramanian - San Jose CA
Minh Van Ngo - Fremont CA
Suzette K. Pangrle - Cupertino CA
Kashmir Sahota - Fremont CA
Christopher F. Lyons - Fremont CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 21302

US Classification:

438624, 438622, 438740, 438723, 438724, 430 5

Abstract:

The present invention provides a method for manufacturing a semiconductor device with a bottom anti-reflective coating (BARC) that acts as an etch stop layer and does not need to be removed. In one embodiment, electrical devices are formed on a semiconductor substrate. Contacts are then formed for each electrical device and a partially UV transparent BARC is then deposited. An inter-layer dielectric (ILD) layer is then formed and then covered with photoresist. A top ARC (TARC) is then added and the photoresist is then photolithographically processed and subsequently developed. The TARC, ILD, and BARC layers are then selectively etched down to the device contacts forming local interconnects. The photoresist and TARC are later removed, but the BARC does not require removal due to its optical transparency.

US Patent:

6380588, Apr 30, 2002

Filed:

May 9, 2000

Appl. No.:

09/567013

Inventors:

William G. En - Milpitas CA
Minh Van Ngo - Union City CA
David K. Foote - San Jose CA
Scott A. Bell - San Jose CA
Olov B. Karlsson - San Jose CA
Christopher F. Lyons - Fremont CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2100

US Classification:

257345, 257327, 438595

Abstract:

A semiconductor device having both functional and non-functional or dummy lines, regions and/or patterns to create a topology that causes the subsequently formed spacers to be more predictable and uniform in shape and size.

US Patent:

6383952, May 7, 2002

Filed:

Feb 28, 2001

Appl. No.:

09/794632

Inventors:

Ramkumar Subramanian - Sunnyvale CA
Bhanwar Singh - Morgan Hill CA
Marina V. Plat - San Jose CA
Christopher F. Lyons - Fremont CA
Scott A. Bell - San Jose CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

H01L 2131

US Classification:

438781, 438780

Abstract:

A method of doubling the frequency of small pattern formation. The method includes forming a photoresist layer, and then patterning it. A RELACS polymer is spread over the patterned photoresist layer. Portions of the RELACS polymer on top portions of each patterned photoresist region are removed, by either etching or by polishing them off. Portions between each patterned photoresist region are also removed in this step. The patterned photoresist regions are removed, preferably by a flood exposure and then application of a developer to the exposed photoresist regions. The remaining RELACS polymer regions, which were disposed against respective sidewalls of the patterned photoresist regions, prior to their removal, are then used for forming small pattern regions to be used in a semiconductor device to be formed on the substrate. These small pattern regions can be used to form separate poly-gates.

US Patent:

6391525, May 21, 2002

Filed:

Jan 13, 2000

Appl. No.:

09/482256

Inventors:

Christopher F. Lyons - Fremont CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G03F 700

US Classification:

430311, 430312, 430314, 430316, 430317, 430318

Abstract:

In one embodiment, the present invention relates to a method of forming a circuit structure containing at least one sub-lithographic gate conductor involving the steps of providing a substrate comprising active regions and a preliminary gate conductor film over portions of the substrate and portions of the active regions; forming a sidewall template mask having at least one sidewall over a portion of the preliminary gate conductor film that is positioned over portions of the active regions; forming a sidewall film over the sidewall template mask, the sidewall film having a vertical portion adjacent the sidewall of the sidewall template mask and a horizontal portion in areas not adjacent the sidewall of the sidewall template mask; removing the horizontal portion of the sidewall film exposing a portion of the sidewall template mask and removing the sidewall template mask; providing a second mask over the portions of the preliminary gate conductor film that are not positioned over portions of the active regions; removing exposed portions of the preliminary gate conductor film thereby forming the circuit structure containing the sub-lithographic gate conductor and gate conductors; providing a trim mask over the active regions, portions of the sub-lithographic gate conductor and the gate conductors; and removing exposed portions of the sidewall film and portions of the preliminary gate conductor film under the sidewall film.

US Patent:

6399284, Jun 4, 2002

Filed:

Jun 18, 1999

Appl. No.:

09/336619

Inventors:

Christopher F. Lyons - Fremont CA

Assignee:

Advanced Micro Devices, Inc. - Sunnyvale CA

International Classification:

G03F 700

US Classification:

430313, 430316, 430317

Abstract:

In one embodiment, the present invention relates to a method of forming a sub-lithographic via or contact, involving the steps of providing a substrate comprising a conductor having a width of about 0. 25 m or less over a portion of the substrate and an insulating film over the conductor and the substrate; etching a preliminary via in the insulating film over the conductor, the preliminary via defined by sidewalls in the insulating film; depositing a CVD layer over the substrate, the insulating film, and the conductor, the CVD layer having a vertical portion adjacent the sidewalls of the insulating film and a horizontal portion in areas not adjacent the sidewalls of the insulating film; removing the horizontal portion of the CVD layer thereby forming the sub-lithographic via over the conductor, and depositing a conductive material into the sub-lithographic via to form a sub-lithographic contact, the sub-lithographic via and/or sub-lithographic contact having a width of less than about 0. 25 m.