Christopher John Mayer

US Patent:

20220255551, Aug 11, 2022

Filed:

May 2, 2022

Appl. No.:

17/734346

Inventors:

- Limerick, IE
Lu WU - Summerfield NC, US
Christopher MAYER - Dover MA, US
Gord ALLAN - Ottawa CA, US

Assignee:

Analog Devices International Unlimited Company - Limerick

International Classification:

H03L 7/093
H03L 7/091
H03L 7/099
H03L 7/185

Abstract:

Embodiments of the present disclosure provide systems and methods for realizing phase synchronization updates based on an input system reference signal SYSREF without the need to synchronously distribute the SYSREF signal on a high-speed domain. In particular, phase synchronization mechanisms of the present disclosure are based on keeping a first phase accumulator in the device clock domain and using a second phase accumulator in the final digital clock domain to asynchronously transmit phase updates to the final digital clock domain. Arrival of a new SYSREF pulse may be detected based on the counter value of the first phase accumulator, which value is asynchronously transferred and scaled to the second phase accumulator downstream. In this manner, even though the SYSREF signal itself is not synchronously transferred to the second phase accumulator, the phase updates from the SYSREF signal may be transferred downstream so that the final phase may be generated deterministically.

US Patent:

20150006775, Jan 1, 2015

Filed:

Jun 28, 2013

Appl. No.:

13/930088

Inventors:

Alexander LEONARD - Greensboro NC, US
Shipra BHAL - Norwood MA, US
Christopher MAYER - Dover MA, US

Assignee:

Analog Devices, Inc. - Norwood MA

International Classification:

G06F 13/16

US Classification:

710112

Abstract:

A circuit may include a queue, a monitor, and a controller. The queue may receive and store a plurality of commands from a plurality of buses to access a shared set of registers. The monitor may monitor the plurality of commands in the queue to determine whether a period of time needs to be reserved for selected commands from one of the plurality of buses. The controller, if the period of time needs to be reserved, based on the period of time determined by the monitor, may disable acceptance of commands from buses other than the one of the plurality of buses, may execute the selected commands for the one of the plurality of buses, and may allow more than one of the plurality of buses access to results of the selected commands.