Christopher E Neely

US Patent:

7852117, Dec 14, 2010

Filed:

Jul 17, 2009

Appl. No.:

12/505239

Inventors:

Jack S. Lo - Santa Clara CA, US
Christopher E. Neely - San Jose CA, US
Gordon J. Brebner - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

H03K 19/0175

US Classification:

326 62, 326 63, 326 41, 326 47

Abstract:

An integrated circuit includes an auto-bridging architecture including a first phases block that interfaces to a first user block having a first user signal domain. The first phases block converts the first user signal domain to a common signal domain. A second phases block coupled to the first phases block interfaces with a second user block having a second user signal domain. The second phases block converts the second user signal domain to the common signal domain so that the first user block cooperates with the second user block through the auto-bridging architecture of the IC.

US Patent:

8121826, Feb 21, 2012

Filed:

Jul 17, 2009

Appl. No.:

12/505243

Inventors:

Christopher E. Neely - San Jose CA, US
Gordon J. Brebner - San Jose CA, US
Jack S. Lo - Santa Clara CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

703 14, 717109, 717104

Abstract:

A design tool for designing a system includes a display device with a first visualization pane showing a symbolic representation of a connection between a first port and a second port of the system and a second visualization pane showing an unconnected port of the system. A text entry pane on the display device shows a textual definition of the connection. An optional status pane shows a textual log of user-performed actions relating to construction of the system.

US Patent:

8560996, Oct 15, 2013

Filed:

Feb 15, 2011

Appl. No.:

13/027667

Inventors:

Gordon J. Brebner - San Jose CA, US
Christopher E. Neely - San Jose CA, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716117, 716116

Abstract:

Approaches for dynamically reconfiguring a programmable integrated circuit (IC) are disclosed. In response to user input to a reconfiguration controller while a circuit is operating in programmable resources of the programmable IC, a replacement module and a module to be replaced in the circuit are selected. A process determines whether or not interfaces of the replacement module are compatible with interfaces of the circuit to the module to be replaced. In response to the interfaces of the replacement module and the interfaces of the circuit to the module to be replaced being compatible, the programmable IC is partially reconfigured with a realization of the replacement module in place of a realization of the module to be replaced.

US Patent:

20130117504, May 9, 2013

Filed:

Nov 8, 2011

Appl. No.:

13/291975

Inventors:

Christopher E. Neely - San Jose CA, US
Gordon J. Brebner - San Jose CA, US

Assignee:

XILINX, INC. - San Jose CA

International Classification:

G06F 12/00

US Classification:

711104, 711E12001

Abstract:

An integrated circuit can include a programmable circuitry operable according to a first clock frequency and a block random access memory. The block random access memory can include a random access memory (RAM) element having at least one data port and a memory processor coupled to the data port of the RAM element and to the programmable circuitry. The memory processor can be operable according to a second clock frequency that is higher than the first clock frequency. Further, the memory processor can be hardwired and dedicated to perform operations in the RAM element of the block random access memory.

US Patent:

7784014, Aug 24, 2010

Filed:

May 3, 2007

Appl. No.:

11/799897

Inventors:

Gordon J. Brebner - Los Gatos CA, US
Christopher E. Neely - San Jose CA, US
Philip B. James-Roxby - Longmont CO, US
Eric R. Keller - Boulder CO, US
Chidamber R. Kulkarni - Santa Clara CA, US
Michael A. Baxter - Sunnyvale CA, US
Henry E. Styles - San Jose CA, US
Graham F. Schelle - Boulder CO, US

Assignee:

Xilinx, Inc. - San Jose CA

International Classification:

G06F 17/50

US Classification:

716 18, 716 17

Abstract:

A method is provided for generating a hardware description language (HDL) specification of a network packet processor from a textual language specification of the processing of network packets by the processor. The processor includes a look-ahead stage, an operation stage, an insert/remove stage, and an interleave stage. The textual language specification identifies the ports of the processor. The textual language specification includes formats for the type or types of the incoming and outgoing network packets. Each format includes the fields of the type of network packet. The textual language specification includes a procedure for each input port and for each type of incoming network packet received at the input port. Each procedure includes one or more actions for modifying the fields of a type of network packet as a function of state data and/or the fields of the type of network packet.