Christopher D Nelson

US Patent:

7849292, Dec 7, 2010

Filed:

Nov 16, 2007

Appl. No.:

11/941900

Inventors:

Matthew William Ashcraft - Belmont CA, US
John Gregory Favor - Scotts Valley CA, US
Christopher Patrick Nelson - Santa Clara CA, US
Ivan Pavle Radivojevic - San Francisco CA, US
Joseph Byron Rowlands - Santa Clara CA, US
Richard Win Thaik - San Jose CA, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G06F 9/00

US Classification:

712220

Abstract:

A method and apparatus for optimizing a sequence of operations adapted for execution by a processor is disclosed to include locating an operation, if any, that is next within the sequence of operations and setting a current operation to be that operation. The current operation is processed as follows: a) de-activating, if not already de-activated, a consumed indicator associated with the current operation; and b) when the current operation is of the producer type, then activating, if not already activated, a producer indicator associated with the current operation, and locating a first set of operations, if any, that i) are earlier in the sequence of operations than the current operation, ii) have their associated producer indicator activated, and iii) have their associated consumed indicator de-activated, and then de-activating the producer indicator associated with each operation in the first set. When the current operation is of the consumer type, then locating a second set of operations, if any, that are earlier in the sequence of operations than the current operation, and then activating, if not already activated, the consumed indicator associated with each operation in the second set.

US Patent:

7937564, May 3, 2011

Filed:

Nov 16, 2007

Appl. No.:

11/941908

Inventors:

Matthew William Ashcraft - Belmont CA, US
John Gregory Favor - Scotts Valley CA, US
Christopher Patrick Nelson - Santa Clara CA, US
Ivan Pavle Radivojevic - San Francisco CA, US
Joseph Byron Rowlands - Santa Clara CA, US
Richard Win Thaik - San Jose CA, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G06F 9/30

US Classification:

712216

Abstract:

A method and apparatus for optimizing a sequence of operations adapted for execution by a processor is disclosed to include associating a symbolic expression with each of at least a subset of the registers, holding a set of dependency indications that specify for each particular symbolic expression which, if any, of the other symbolic expressions must be emitted as operations prior to emitting the particular symbolic expression, locating an operation, if any, that is next within the sequence of operations and setting that operation to be a working operation and processing the working operation. Processing is performed by handling the working operation by a combination of updating zero or more of the symbolic expressions and emitting zero or more of the symbolic expressions as operations, identifying which, if any, of the symbolic expressions that were updated in process were updated such that they must be emitted prior to which other, if any, of the symbolic expressions, and then updating the dependency indicators to include any such dependencies, and identifying which, if any, of the symbolic expressions that were updated in process were updated such that they no longer need to be emitted prior to which other, if any, of the symbolic expressions, and then updating the dependency indicators to remove any such dependencies.

US Patent:

8499293, Jul 30, 2013

Filed:

Nov 16, 2007

Appl. No.:

11/941912

Inventors:

Matthew William Ashcraft - Belmont CA, US
John Gregory Favor - Scotts Valley CA, US
Christopher Patrick Nelson - Santa Clara CA, US
Ivan Pavle Radivojevic - San Francisco CA, US
Joseph Byron Rowlands - Santa Clara CA, US
Richard Win Thaik - San Jose CA, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G06F 9/45

US Classification:

717151, 717152, 717154

Abstract:

A method and apparatus for optimizing a sequence of operations adapted for execution by a processor is disclosed to include associating with each register a symbolic expression selected from a set of possible symbolic expressions, locating an operation, if any, that is next within the sequence of operations and setting that operation to be a working operation, where the working operation has associated therewith a destination register and zero or more source registers, and processing the working operation when the working operation and any symbolic expressions of its source registers, if any, match at least one of a set of rules, where each rule specifies that the working operation must match a subset of the operation set, where each rule also specifies that the symbolic expressions, if any, of any source registers of the working operation must match a subset of the possible symbolic expressions, and where the rule also specifies a result, then posting the result as the symbolic expression of the destination register.

US Patent:

20180371314, Dec 27, 2018

Filed:

Dec 22, 2016

Appl. No.:

16/063660

Inventors:

- Pleasanton CA, US
Hannes Kirzinger - Puergen, DE
Thomas Meier - Munich, DE
Christopher Nelson - Redwood City CA, US

International Classification:

C09K 11/07
C12Q 1/686
C12Q 1/6806

Abstract:

The present disclosure provides an aqueous composition comprising a purified thermostable polypeptide with biological activity, and a purified thermolabile water-soluble substance which in a functional conformation at a permissive temperature absorbs light and/or exhibits fluorescence, wherein the maximal permissive temperature of the polypeptide is above the maximal permissive temperature of the substance. The present disclosure further provides methods employing such a composition, and kits containing ingredients to form such a composition.

US Patent:

20140189457, Jul 3, 2014

Filed:

Dec 27, 2012

Appl. No.:

13/728741

Inventors:

Tak M. Mak - Union City CA, US
Christopher J. Nelson - Gilbert AZ, US
David J. Zimmerman - El Dorado Hills CA, US
Derek B. Feltham - Portland OR, US

International Classification:

G01R 31/3177

US Classification:

714745

Abstract:

I/O delay testing for devices utilizing on-chip delay generation. An embodiment of an apparatus includes I/O buffer circuits, at least one of the buffer circuits including a transmitter and a receiver that are coupled for loop-back testing of the buffer circuit; and testing circuitry for the loop-back testing for the at least one buffer circuit, the loop-back testing including determining whether test data transmitted by the transmitter of the buffer circuit matches test data received by the respective coupled receiver. The testing circuitry includes a delay line to provide delay values from a transmit clock signal for the testing of the at least one buffer circuit, a counter to provide a count to choose one of the plurality of delay values, and test logic for the loop-back testing.