Christopher Emile Nelson

US Patent:

20180096971, Apr 5, 2018

Filed:

Sep 30, 2016

Appl. No.:

15/283055

Inventors:

- Santa Clara CA, US
KALYAN C. KOLLURU - Portland OR, US
PETE D. VOGT - Boulder CO, US
CHRISTOPHER J. NELSON - Gilbert AZ, US
AMANDE B. TRANG - Phoenix AZ, US
UDDALAK BHATTACHARYA - Beaverton OR, US

International Classification:

H01L 25/065
H01L 25/18
G11C 11/4096

Abstract:

In accordance with disclosed embodiments, there are provided systems, methods, and apparatuses for implementing die recovery in Two-Level Memory (2LM) stacked die subsystems. For instance, there is disclosed in accordance with one embodiment a stacked semiconductor package having therein: a processor functional silicon die at a first layer of the stacked semiconductor package; one or more memory dies forming a corresponding one or more memory layers of the stacked semiconductor package; a plurality of Through Silicon Vias (TSVs) formed through the one or more memory dies, wherein each of the plurality of TSVs traverse through the one or more memory layers to the processor functional silicon die at the first layer of the stacked semiconductor package; a plurality of physical memory interfaces electrically interfacing the one or more memory dies to the processor functional silicon die at the first layer through the memory layers via the plurality of TSVs; a redundant physical memory interface formed by a redundant TSV traversing through the memory layers to the processor functional silicon die at the first layer through which to reroute a memory signal path from a defective physical memory interface at a defective TSV to a functional signal path traversing the redundant TSV. Other related embodiments are disclosed.

US Patent:

20150377967, Dec 31, 2015

Filed:

Jun 30, 2014

Appl. No.:

14/319528

Inventors:

BHARANI THIRUVENGADAM - Beaverton OR, US
CHRISTOPHER NELSON - Gilbert AZ, US

International Classification:

G01R 31/317
G01R 31/3177

Abstract:

Testing I/O (input/output) eye width for an interface with an inverted modulated strobe or clock signal. An I/O interface includes multiple signal lines, each with a hardware I/O buffer with timing characteristics. A system generates a strobe signal with a triggering edge that triggers a write, and a trailing edge that is modulated by adjusting the duty cycle of the strobe signal. The system inverts the modulated strobe signal to generate an inverted strobe signal, wherein the inverted strobe signal has a modulated triggering edge generated from inverting the modulated trailing edge. The device under test writes test data based on the triggering edge of the original strobe signal and reads test data based on the triggering edge of the inverted strobe signal.