Christopher J Nelson

US Patent:

6693436, Feb 17, 2004

Filed:

Dec 23, 1999

Appl. No.:

09/471638

Inventors:

Christopher J. Nelson - Chandler AZ

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01R 3126

US Classification:

324537, 324763, 324765, 326 16, 714731

Abstract:

An output-relative signal receiver to test an integrated circuit that provides an output-relative data signal. The output-relative signal receiver receives the output-relative data signal and a corresponding output strobe signal from an integrated circuit device and produces a test strobe signal derived from the output strobe signal. The test strobe signal is used to test a feature of the integrated circuit device indicated by the output-relative data signal.

US Patent:

6768297, Jul 27, 2004

Filed:

Nov 29, 2000

Appl. No.:

09/725401

Inventors:

John C. Johnson - Phoenix AZ
Christopher J. Nelson - Gilbert AZ
Donald E. Edenfeld - Beaverton OR

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G01R 3128

US Classification:

3241581, 324 731, 714726

Abstract:

A tester for testing a digital device. The tester includes a plurality of time measurement units to measure transition timing values of output data of each output pin of the digital device in each test cycle. A plurality of result operations units performs real-time arithmetic operations on the measured transition timing values to produce a pass/fail result and additional test results. A plurality of result accumulators stores the pass/fail result and a number of selected test results. And a capture/analysis engine captures and analyzes the pass/fail result and the selected results to provide comprehensive test performance of the digital device.

US Patent:

50945572, Mar 10, 1992

Filed:

Dec 8, 1989

Appl. No.:

7/448080

Inventors:

Peter K. Nelson - Phoenix AZ
Christopher F. Nelson - Phoenix AZ

International Classification:

A46B 1100
A46B 1500

US Classification:

401 11

Abstract:

A golf club handle renovating device for cleaning and for removing an outer, weather-hardened rubber surface of a golf club handle to expose an underlying supply rubber surface includes a tube containing a plurality of stiff plastic blades attached at one end to the inner surface of the tube. The blades project inwardly from the inner surface of the tube so that a second end of the blades define a longitudinal central void adapted to closely receive the handle therein.

US Patent:

20180096979, Apr 5, 2018

Filed:

Mar 31, 2017

Appl. No.:

15/475879

Inventors:

- Santa Clara CA, US
BARUCH SCHNARCH - Zichron-Ya'akov, IL
CHRISTOPHER J. NELSON - Gilbert AZ, US
DANKA GOLDIN SCHWABOVA - Haifa, IL

International Classification:

H01L 25/18
H01L 25/065
H01L 21/66
G11C 11/4093
G11C 11/4076
G11C 29/00
G11C 11/4096

Abstract:

A stacked semiconductor package comprising a functional silicon die having embedded thereupon a Wide Input/Output 2 (WIO2) interface, and two or more memory dies forming a corresponding two or more memory layers of the stacked semiconductor package. A plurality of Through Silicon Vias (TSVs) are formed through the two or more memory dies, wherein each of the plurality of TSVs traverse through the two or more memory layers to the functional silicon die via the WIO2 interface of the functional silicon die. A test port interface receives test signals from an external tester and routes the test signals through a steering logic communicably interfaced with the two or more memory dies. The steering logic shifts data into and out of the two or more memory dies through the plurality of TSVs.

US Patent:

20170301625, Oct 19, 2017

Filed:

Jun 28, 2017

Appl. No.:

15/636117

Inventors:

- Santa Clara CA, US
Christopher J. Nelson - Gilbert AZ, US
Omkar G. Karhade - Chandler AZ, US
Feras Eid - Chandler AZ, US
Nitin A. Deshpande - Chandler AZ, US
Shawna M. Liff - Scottsdale AZ, US

International Classification:

H01L 23/538
H01L 23/31
H01L 23/367
H01L 25/065

Abstract:

Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.

US Patent:

20160300824, Oct 13, 2016

Filed:

Jun 15, 2016

Appl. No.:

15/183179

Inventors:

- Santa Clara CA, US
John S. Guzek - Chandler AZ, US
Johanna M. Swan - Scottsdale AZ, US
Christopher J. Nelson - Gilbert AZ, US
Nitin A. Deshpande - Chandler AZ, US
William J. Lambert - Chandler AZ, US
Charles A. Gealer - Phoenix AZ, US
Feras Eid - Chandler AZ, US
Islam A. Salama - Chandler AZ, US
Kemal Aygun - Chandler AZ, US
Sasha N. Oster - Chandler AZ, US
Tyler N. Osborn - Gilbert AZ, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

H01L 25/16
H01L 23/538
H01L 23/00
H01L 25/065

Abstract:

A microelectronic package of the present description may comprises a first microelectronic device having at least one row of connection structures electrically connected thereto and a second microelectronic device having at least one row of connection structures electrically connected thereto, wherein the connection structures within the at least one first microelectronic device row are aligned with corresponding connection structures within the at least one second microelectronic device row in an x-direction. An interconnect comprising an interconnect substrate having a plurality of electrically isolated conductive traces extending in the x-direction on a first surface of the interconnect substrate may be attached to the at least one first microelectronic device connection structure row and the at least one second microelectronic device connection structure row, such that at least one interconnect conductive trace forms a connection between a first microelectronic device connection structure and its corresponding second microelectronic device connection structure.

US Patent:

20160155705, Jun 2, 2016

Filed:

Jan 22, 2016

Appl. No.:

15/004774

Inventors:

- Santa Clara CA, US
Christopher J. Nelson - Gilbert AZ, US
Omkar G. Karhade - Chandler AZ, US
Feras Eid - Chandler AZ, US
Nitin A. Deshpande - Chandler AZ, US
Shawna M. Liff - Scottsdale AZ, US

International Classification:

H01L 23/538
H01L 23/367
H01L 21/56

Abstract:

Embodiments of the present disclosure are directed towards an integrated circuit (IC) package having first and second dies with first and second input/output (I/O) interconnect structures, respectively. The IC package may include a bridge having first and second electrical routing features coupled to a portion of the first and second I/O interconnect structures, respectively. In embodiments, the first and second electrical routing features may be disposed on one side of the bridge; and third electrical routing features may be disposed on an opposite side. The first and second electrical routing features may be configured to route electrical signals between the first die and the second die and the third electrical routing features may be configured to route electrical signals between the one side and the opposite side. The first die, the second die, and the bridge may be embedded in electrically insulating material. Other embodiments may be described and/or claimed.

US Patent:

20150324265, Nov 12, 2015

Filed:

May 6, 2014

Appl. No.:

14/270503

Inventors:

CHRISTOPHER NELSON - Gilbert AZ, US
BHARANI THIRUVENGADAM - Beaverton OR, US

International Classification:

G06F 11/263
G06F 11/22

Abstract:

Indirect testing of multiple I/O interface signal lines concurrently. A system distributes a test data sequence to a group of signal lines. Each signal line receives the test data sequence and checks for errors in receiving the test data sequence at an associated I/O buffer. The system includes an error detection mechanism for each signal line. The system also includes an error detection mechanism for the group of multiple signal lines. If the I/O buffer receives any bit of the test data sequence incorrectly, the signal line error detection indicates an error. The group error detection accumulates pass/fail information for all signal lines in the group. Rather than sending a pass/fail indication on every cycle of the test, the group error detection can count pass/fail information for all signal lines of the group for all bits of the test data sequence and indicate error results after the entire test data is received.