Christopher M Neumann

US Patent:

7720247, May 18, 2010

Filed:

Aug 31, 2005

Appl. No.:

11/217115

Inventors:

Brian D. Castro - Hermosa Beach CA, US
Tien Whei Din - Carson CA, US
Christopher Neumann - Granada Hills CA, US

Assignee:

Harman International Industries, Incorporated - Northridge CA

International Classification:

H04R 1/02

US Classification:

381395, 381386

Abstract:

A loudspeaker mounting assembly for mounting a loudspeaker in an isolated relation to a structure includes an enclosure and a plurality of interface elements composed of a vibration-damping material. The enclosure has an interior for receiving the loudspeaker and includes at least two spaced-apart support members. Each of the at least two support members includes a support member outer surface and an inner surface extending from the support member outer surface into the support member. The inner surface defines a support member bore. Each interface element includes an interface element outer surface. Each interface element is disposed in a corresponding one of the support member bores and at least partially extends out from the respective support member outer surface, where each interface element outer surface contacts the respective inner surface of the support member.

US Patent:

8630438, Jan 14, 2014

Filed:

Apr 29, 2010

Appl. No.:

12/769762

Inventors:

Brian D. Castro - Hermosa Beach CA, US
Christopher Neumann - Granada Hills CA, US

Assignee:

Harman International Industries, Incorporated - Stamford CT

International Classification:

H04R 1/02
H05K 5/00

US Classification:

381386, 181150

Abstract:

A loudspeaker mounting assembly for mounting a loudspeaker in an isolated relation to a structure includes an enclosure and a plurality of interface elements composed of a vibration-damping material. The enclosure has an interior for receiving the loudspeaker and includes at least two spaced-apart support members. Each of the at least two support members includes a support member outer surface and an inner surface extending from the support member outer surface into the support member. The inner surface defines a support member bore. Each interface element includes an interface element outer surface. Each interface element is disposed in a corresponding one of the support member bores and at least partially extends out from the respective support member outer surface, where each interface element outer surface contacts the respective inner surface of the support member.

US Patent:

D476641, Jul 1, 2003

Filed:

Jun 6, 2002

Appl. No.:

29/161843

Inventors:

Brian D. Castro - Hermosa Beach CA
Christopher Neumann - Granada Hills CA
Timothy Prenta - Simi Valley CA

Assignee:

Harman International Industries, Incorporated - Northridge CA

International Classification:

1401

US Classification:

D14215, D14214

US Patent:

20230100860, Mar 30, 2023

Filed:

Sep 24, 2021

Appl. No.:

17/485306

Inventors:

- Santa Clara CA, US
Shriram SHIVARAMAN - Hillsboro OR, US
Uygar E. AVCI - Portland OR, US
Sarah ATANASOV - Beaverton OR, US
Christopher M. NEUMANN - Portland OR, US

International Classification:

H01L 27/11507
H01L 27/108
H01L 25/065

Abstract:

Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to memory devices utilizing dead-layer-free materials to reduce disturb effects. Other embodiments may be described or claimed.

US Patent:

20230101111, Mar 30, 2023

Filed:

Sep 24, 2021

Appl. No.:

17/485317

Inventors:

- Santa Clara CA, US
Uygar E. AVCI - Portland OR, US
Sarah ATANASOV - Beaverton OR, US
Jason PECK - Hillsboro OR, US
Christopher M. NEUMANN - Portland OR, US

International Classification:

H01L 27/11514
H01L 27/11507

Abstract:

Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to three-dimensional ferroelectric random access memory (3D FRAM) devices with a sense transistor coupled to a plurality of capacitors to (among other things) help improve signal levels and scaling. Other embodiments may be disclosed or claimed.

US Patent:

20210407999, Dec 30, 2021

Filed:

Jun 26, 2020

Appl. No.:

16/913796

Inventors:

- Santa Clara CA, US
Gilbert DEWEY - Beaverton OR, US
Anh PHAN - Beaverton OR, US
Nicole K. THOMAS - Portland OR, US
Urusa ALAAN - Hillsboro OR, US
Seung Hoon SUNG - Portland OR, US
Christopher M. NEUMANN - Portland OR, US
Willy RACHMADY - Beaverton OR, US
Patrick MORROW - Portland OR, US
Hui Jae YOO - Portland OR, US
Richard E. SCHENKER - Portland OR, US
Marko RADOSAVLJEVIC - Portland OR, US
Jack T. KAVALIEROS - Portland OR, US
Ehren MANNEBACH - Beaverton OR, US

International Classification:

H01L 27/092
H01L 29/06
H01L 29/78
H01L 29/775
H01L 29/423

Abstract:

Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.