Christopher M Neumann

US Patent:

20230100860, Mar 30, 2023

Filed:

Sep 24, 2021

Appl. No.:

17/485306

Inventors:

- Santa Clara CA, US
Shriram SHIVARAMAN - Hillsboro OR, US
Uygar E. AVCI - Portland OR, US
Sarah ATANASOV - Beaverton OR, US
Christopher M. NEUMANN - Portland OR, US

International Classification:

H01L 27/11507
H01L 27/108
H01L 25/065

Abstract:

Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to memory devices utilizing dead-layer-free materials to reduce disturb effects. Other embodiments may be described or claimed.

US Patent:

20230101111, Mar 30, 2023

Filed:

Sep 24, 2021

Appl. No.:

17/485317

Inventors:

- Santa Clara CA, US
Uygar E. AVCI - Portland OR, US
Sarah ATANASOV - Beaverton OR, US
Jason PECK - Hillsboro OR, US
Christopher M. NEUMANN - Portland OR, US

International Classification:

H01L 27/11514
H01L 27/11507

Abstract:

Embodiments of the disclosure are directed to advanced integrated circuit structure fabrication and, in particular, to three-dimensional ferroelectric random access memory (3D FRAM) devices with a sense transistor coupled to a plurality of capacitors to (among other things) help improve signal levels and scaling. Other embodiments may be disclosed or claimed.

US Patent:

20210407999, Dec 30, 2021

Filed:

Jun 26, 2020

Appl. No.:

16/913796

Inventors:

- Santa Clara CA, US
Gilbert DEWEY - Beaverton OR, US
Anh PHAN - Beaverton OR, US
Nicole K. THOMAS - Portland OR, US
Urusa ALAAN - Hillsboro OR, US
Seung Hoon SUNG - Portland OR, US
Christopher M. NEUMANN - Portland OR, US
Willy RACHMADY - Beaverton OR, US
Patrick MORROW - Portland OR, US
Hui Jae YOO - Portland OR, US
Richard E. SCHENKER - Portland OR, US
Marko RADOSAVLJEVIC - Portland OR, US
Jack T. KAVALIEROS - Portland OR, US
Ehren MANNEBACH - Beaverton OR, US

International Classification:

H01L 27/092
H01L 29/06
H01L 29/78
H01L 29/775
H01L 29/423

Abstract:

Embodiments disclosed herein include stacked forksheet transistor devices, and methods of fabricating stacked forksheet transistor devices. In an example, an integrated circuit structure includes a backbone. A first transistor device includes a first vertical stack of semiconductor channels adjacent to an edge of the backbone. A second transistor device includes a second vertical stack of semiconductor channels adjacent to the edge of the backbone. The second transistor device is stacked on the first transistor device.