Christopher Thomas O'Brien

US Patent:

20090097853, Apr 16, 2009

Filed:

Oct 12, 2007

Appl. No.:

11/871973

Inventors:

Anthony L. Sasak - Arlington Height IL, US
Christopher V. O'Brien - North Aurora IL, US

International Classification:

H04J 14/08
H04J 3/00
H04L 29/10

US Classification:

398 98, 370498, 370216

Abstract:

A method includes storing a value of shared variables from a first active packet-to-tdm interface. The value of the shared variables is provided to a successor active packet-to-tdm interface.

US Patent:

20170373981, Dec 28, 2017

Filed:

Sep 11, 2017

Appl. No.:

15/700810

Inventors:

- Naperville IL, US
Christopher V. O'Brien - North Aurora IL, US

Assignee:

Tellabs Operations, Inc. - Naperville IL

International Classification:

H04L 12/841
H04L 12/863
H04J 3/06
H04J 3/14
H04L 12/24
H04L 12/26

Abstract:

A network device such as a router or switch, in one embodiment, includes a timing analyzer which is capable of providing timing analysis over one or more network circuits. The timing analyzer, in one aspect, receives a data packet traveling across a circuit emulation service (“CES”) circuit such as T1 or E1 circuit. Upon obtaining an arrival timestamp associated with the data packet, the arrival timestamp is stored in a timestamp buffer in accordance with a first-in first-out (“FIFO”) storage sequence. After identifying the oldest arrival timestamp in the timestamp buffer, an offset is generated based on the result of comparison between the arrival timestamp and the oldest timestamp. The timing analyzer can also be configured to generate timing reports on-demand based on generated offset(s).

US Patent:

20140307746, Oct 16, 2014

Filed:

Apr 11, 2013

Appl. No.:

13/861187

Inventors:

- Naperville CA, US
Christopher V. O'Brien - North Aurora IL, US

Assignee:

Tellabs Operations, Inc. - Naperville IL

International Classification:

H04J 3/06

US Classification:

370413, 370412, 370415

Abstract:

A network device such as a router or switch, in one embodiment, includes a timing analyzer which is capable of providing timing analysis over one or more network circuits. The timing analyzer, in one aspect, receives a data packet traveling across a circuit emulation service (“CES”) circuit such as T1 or E1 circuit. Upon obtaining an arrival timestamp associated with the data packet, the arrival timestamp is stored in a timestamp buffer in accordance with a first-in first-out (“FIFO”) storage sequence. After identifying the oldest arrival timestamp in the timestamp buffer, an offset is generated based on the result of comparison between the arrival timestamp and the oldest timestamp. The timing analyzer can also be configured to generate timing reports on-demand based on generated offset(s).