Christopher Michael Olson

US Patent:

7528097, May 5, 2009

Filed:

Aug 4, 2005

Appl. No.:

11/198006

Inventors:

Francis V. Hanson - Salt Lake City UT, US
John V. Fletcher - Murray UT, US
Alyssa M. Redding - Concord CA, US
Christopher Olson - Tooele UT, US
Jumpol Jaturapitpornsakul - Salt Lake City UT, US

Assignee:

University of Utah Research Foundation - Salt Lake City UT

International Classification:

C10M 169/04

US Classification:

508491, 210922, 210923, 210924, 210925

Abstract:

A composition and method for a non-emulsion crude oil simulant containing biodegradable oil, and a terpene is disclosed and described. Biodegradable oils such as canola oil, cottonseed oil, and soybean oil can be particularly beneficial for use in connection with these oil simulants. Terpenes such as d-limonene can be included to provide oil simulant compositions which exhibit good oil simulant properties. Additives such as photochromic dyes, food dyes, food-grade antioxidants, microorganisms, and nutrients can also be used. These non-emulsion based oil simulants can be readily tailored and adjusted to approximate relevant properties of a specific target fluid for use in assessing oil spill response, containment, clean-up of equipment, percolation, and/or spill behavior.

US Patent:

58154060, Sep 29, 1998

Filed:

Mar 25, 1996

Appl. No.:

8/620734

Inventors:

Robert Thaddeus Golla - Plano TX
Christopher Hans Olson - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 1700

US Classification:

364490

Abstract:

A timing driven placement system and method for designing an integrated circuit. The inventive method includes the steps of identifying a plurality of nets having blocks of circuit components connected by conductive elements and assigning weights to the nets in proportion to timing and resistive-capacitive (RC) effects therein. In the preferred embodiment, the weights are used by a conventional placement program to obtain the final placements.

US Patent:

56341032, May 27, 1997

Filed:

Nov 9, 1995

Appl. No.:

8/555819

Inventors:

Carl D. Dietz - Frisco TX
Robert T. Golla - Plano TX
Christopher H. Olson - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 932

US Classification:

395582

Abstract:

A method and system within a processor are disclosed for executing selected instructions among a number of instructions stored within a memory, wherein the processor has a maximum of instructions that can dispatched for execution during each processor cycle. A subset of the instructions are fetched from the memory for execution. A determination is then made whether the set of instructions includes an unresolved branch instruction. In response to a determination that the set of instructions includes an unresolved branch instruction, a prediction is made whether a branch indicated by the branch instruction will be taken or will not be taken. In response to a prediction that the branch will be taken, a nonsequential target instruction indicated by the branch instruction is fetched from memory. A determination is made whether the maximum number of instructions can be dispatched for execution during a processor cycle subsequent to the branch prediction without dispatching instructions within the sequential execution path. In response to a determination that less than the maximum number of target instructions can be dispatched in the processor cycle subsequent to the branch prediction without dispatching instructions within the sequential execution path, an instruction within the sequential execution path is speculatively dispatched for execution.

US Patent:

57940240, Aug 11, 1998

Filed:

Mar 25, 1996

Appl. No.:

8/621552

Inventors:

Robert Thaddeus Golla - Plano TX
Thomas Alan Hoy - Austin TX
Christopher Hans Olson - Austin TX
Terence Matthew Potter - Austin TX
Thomas Luther Thomas - Austin TX

Assignee:

International Business Machines Corporation - Armonk NY

International Classification:

G06F 930

US Classification:

395569

Abstract:

A method and system for dynamically recovering a lookahead register-address-table (RAT) in a processor that executes program instructions. Each instruction that updates a logical register address is assigned to a different physical register address. Each of the instructions to be processed by the processor are stored in a fifo queue. The physical register address assignments for each of the instructions are stored in a first RAT, and information regarding instructions that have completed execution by the processor are stored in a second RAT. The method and system further comprises storing the physical register address assignments for non-branch instructions from the fifo queue in a recovery RAT. The first RAT is then restored after an interrupt occurs by copying the second RAT into the recovery RAT and then copying the recovery RAT into the first RAT. The first RAT is restored after a mispredicted branch instruction has been executed by copying the recovery RAT into the first RAT, whereby the first RAT is restored without storing multiple snapshots.