Christopher J Olson

US Patent:

6361645, Mar 26, 2002

Filed:

Oct 8, 1998

Appl. No.:

09/169017

Inventors:

Alan M. Schoepp - Ben Lomond CA
Robert E. Knop - Fremont CA
Christopher H. Olson - El Dorado CA
Michael S. Barnes - San Ramon CA
Tuan M. Ngo - Milpitas CA

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

H02N 1300

US Classification:

156345, 118723 E, 118728, 118500, 20429803, 20429808, 20429832, 20429834, 361234, 323234, 323304, 323318, 324109

Abstract:

Disclosed is a method and device for compensating a bias voltage on a wafer disposed over an electrostatic chuck in a processing chamber of a plasma processing system. The plasma processing system includes an electrostatic and RF power supplies that are coupled to the electrostatic chuck. The bias compensation device includes a voltage converter, a storage unit, and a voltage adjusting circuitry. The voltage converter is coupled to the electrostatic chuck for detecting a voltage Vpp of the electrostatic chuck. The voltage converter converts the detected voltage to a lower voltage Vref. The storage unit stores a predetermined slope and a predetermined offset of a calibration curve, which is derived by fitting a plurality of wafer bias voltages as a function of electrostatic chuck voltages.

US Patent:

8195923, Jun 5, 2012

Filed:

Apr 7, 2009

Appl. No.:

12/420054

Inventors:

Lawrence A. Spracklen - Boulder Creek CA, US
Gregory F. Grohoski - Bee Cave TX, US
Christopher H. Olson - Austin TX, US
Robert T. Golla - Round Rock TX, US

Assignee:

Oracle America, Inc. - Redwood City CA

International Classification:

G06F 9/30

US Classification:

712209, 712208

Abstract:

Systems and methods for efficient instruction support of an multiple features for opcodes of an instruction set. A processor detects a fetched instruction of a computer program comprises an opcode corresponding to a plurality of functions. Each function corresponds to a different type of operation. The processor determines the received instruction corresponds to a feature requested by the computer program, such as a cryptographic algorithm. A determination is made as to whether hardware support exists for the feature. If hardware support exists for the feature, the instruction is executed on-chip by the hardware. Otherwise, software performs the operation corresponding to the instruction.

US Patent:

20100329450, Dec 30, 2010

Filed:

Jun 30, 2009

Appl. No.:

12/494481

Inventors:

Leonard D. Rarick - San Jose CA, US
Christopher H. Olson - Austin TX, US
Gregory F. Grohoski - Bee Cave TX, US

Assignee:

SUN MICROSYSTEMS, INC. - Santa Clara CA

International Classification:

H04L 9/06

US Classification:

380 29

Abstract:

Some embodiments of the present invention provide a processor, which includes a set of general-purpose registers and at least one execution unit. Each general-purpose register in the set of general-purpose registers is at least 64 bits wide, and the execution unit supports one or more Data Encryption Standard (DES) instructions. Specifically, the execution unit may support a permutation-rotation instruction for performing DES permutation operations and DES rotation operations. The execution unit may also support a round instruction to perform a DES round operation. Since the DES instructions use general-purpose registers instead of special-purpose registers to perform DES-specific operations, the processor's circuit complexity and area are reduced. Furthermore, in some embodiments, since the DES instructions require at most two operands, the number of bits required to specify the location of the operands are reduced, thereby enabling a larger number of instructions to be supported by the processor.

US Patent:

20110091035, Apr 21, 2011

Filed:

Oct 20, 2009

Appl. No.:

12/582299

Inventors:

Lawrence Spracklen - Boulder Creek CA, US
Farnad Sajjadian - Sunnyvale CA, US
Christopher H. Olson - Austin TX, US
Sanjay Patel - Fremont CA, US

Assignee:

SUN MICROSYSTEMS, INC. - Santa Clara CA

International Classification:

H04L 9/18

US Classification:

380 37, 380 44

Abstract:

A system including a memory; a software interface, operatively connected to the memory, and configured to generate a modified version of a confidentially key (CKey), and a modified version of an integrity key (IKey); and a Kasumi engine having a hardware implementation of a Kasumi cipher and configured to load the modified version of the CKey from the memory to perform a confidentiality function, and to load the modified version of the IKey from memory to perform an integrity function.

US Patent:

57586802, Jun 2, 1998

Filed:

Mar 29, 1996

Appl. No.:

8/627712

Inventors:

Farro Frank Kaveh - Mountain View CA
Michael S. Barnes - San Francisco CA
Brett C. Richardson - San Ramon CA
Christopher H. Olson - El Dorado CA

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

F17D 116
F17D 118
F16K 1734

US Classification:

137 14

Abstract:

A method and apparatus is disclosed for controlling the pressure of reaction chamber in wafer processing equipment. The disclosed apparatus and method uses a ballast port for inserting gas into the evacuation system, thereby controlling the pressure in the reaction chamber. The disclosed apparatus and method further uses estimation curves to estimate the desired position of a controlled gate valve which is located between the reaction chamber and turbo pump. The disclosed apparatus and method further introduces process gases at higher rate than set point levels to reduce the transition time or stabilization time required when raising the pressure in the reaction chamber.

US Patent:

58031073, Sep 8, 1998

Filed:

Mar 29, 1996

Appl. No.:

8/627711

Inventors:

Farro Frank Kaveh - Mountain View CA
Michael S. Barnes - San Francisco CA
Brett C. Richardson - San Ramon CA
Christopher H. Olson - El Dorado CA

Assignee:

Lam Research Corporation - Fremont CA

International Classification:

F17D 116
F17D 118
F16K 1734

US Classification:

137 14

Abstract:

A method and apparatus is disclosed for controlling the pressure of reaction chamber in wafer processing equipment. The disclosed apparatus and method uses a ballast port for inserting gas into the evacuation system, thereby controlling the pressure in the reaction chamber. The disclosed apparatus and method further uses estimation curves to estimate the desired position of a controlled gate valve which is located between the reaction chamber and turbo pump. The disclosed apparatus and method further introduces process gases at higher rate than set point levels to reduce the transition time or stabilization time required when raising the pressure in the reaction chamber.