Bank of America Dec 2016 - Jan 2018
Home Equity Specialist
Bank of America Dec 2016 - Jan 2018
Loan Officer
St. Joseph's Hospital and Medical Center Feb 1, 2015 - Dec 2016
Orthopedic Assistant
Toca (The Orthopedic Clinic Association) Jan 2010 - Feb 2015
Orthopedic Assistant
The Core Institute Jan 2005 - Dec 2009
Dme Supervisor
Education:
Arizona State University 2008 - 2010
Associates, Psychology
Kaplan College - Phoenix 2005 - 2006
Associates
Bradshaw Mountain High School 2000 - 2004
Skills:
Orthopedics Healthcare Sports Surgery Customer Service Hospitals Cpr Certified Clinical Research Rehabilitation Sports Medicine Treatment Healthcare Management Medicine Medical Education Emr Healthcare Information Technology Pediatrics Medical Devices Sports Injuries Physical Therapy Pain Management Medical Terminology Musculoskeletal Public Health Social Media Spine Microsoft Office Teamwork Microsoft Excel Physicians Biomechanics Injury Prevention Data Entry Athletic Training Time Management Board Certified Injury Microsoft Word Health Education Athletics Manual Therapy Prevention Sales Operations Fitness Product Launch Exercise Physiology Powerpoint Event Management Wellness Diabetes
Interests:
Children Environment Education Human Rights Animal Welfare Health
Christopher A. Parris - Casa Grande AZ, US Robert S. Green - Tucson AZ, US David L. Wilkie - Gilbert AZ, US Martin R. Bowman - Gilbert AZ, US Alex Martinez - Mesa AZ, US Martin S. Kvasnicka - Gilbert AZ, US
Assignee:
Microchip Technology Incorporated - Chandler AZ
International Classification:
G06F 13/00
US Classification:
710110, 710105
Abstract:
An integrated circuit digital device, acting as a master, communicates with at least one peripheral device, acting as a slave, using an enhanced single-node protocol for data, address and control operation. The peripheral device may be selected from any number of different functions. The peripheral device may be packaged in a low pin count integrated circuit package. At a minimum, the peripheral device integrated circuit package may have a ground terminal, V; a power terminal, Vor V; and a bidirectional serial clock, and data and control input-output (SCIO) terminal. Acknowledgment sequences from both the master and slave devices ensure robust communications therebetween.
Memory Using A Single-Node Data, Address And Control Bus
Peter H. Sorrells - Gilbert AZ, US David L. Wilkie - Gilbert AZ, US Christopher A. Parris - Casa Grande AZ, US Martin S. Kvasnicka - Gilbert AZ, US Martin R. Bowman - Chandler AZ, US
Assignee:
Microchip Technology Incorporated - Chandler AZ
International Classification:
G11C 16/04
US Classification:
36518901, 36518904, 36518905, 36518911, 36518918
Abstract:
An integrated circuit digital device is coupled to a memory with a single-node data, address and control bus. The memory may be a non-volatile memory and/or volatile memory. The memory may be packaged in a low pin count integrated circuit package. The memory integrated circuit package may have a ground terminal, V; a power terminal, Vor V; and a bidirectional serial input-output (I/O) terminal, SCIO. Memory block address set-up may be performed via software instructions through the SCIO terminal. In addition, hardwired memory block address selection terminals A and A may be used when more then three terminals are available on the memory integrated circuit package. The memory may have active pull-up and pull-down drivers coupled to the single-node data, address and control bus.