Christopher S Read

US Patent:

56066775, Feb 25, 1997

Filed:

Jun 7, 1995

Appl. No.:

8/472828

Inventors:

Keith Balmer - Bedford, GB2
Christopher J. Read - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 744

US Classification:

395384

Abstract:

This invention is a method and apparatus for multiplication which enables two factors to be packed into the same size data word as the product. The invention partitions two N bit buses (210, 202) into a first set of M bits and a second set of L bits. In the preferred embodiment the first set of M bits is N/2 most significant bits and the second set of L bits in N/2 least significant bits. Thus N=M+L and M=L. A multiplier (220) multiplies the second sets of L bits of each of the N bit numbers. This results in a product having up to 2L bits. The invention forms an output word having a first set of L bits being the most significant L bits of the product and a second set of M bits being the first set of M bits of the first N bit data word. In the preferred embodiment, a multiplexer (221) selects between the full product of 2L bits and the packed word output. The product may be scaled prior to partitioning via a left shifter (224) which shifts the product a selected number of bit positions.

US Patent:

55128963, Apr 30, 1996

Filed:

Nov 30, 1993

Appl. No.:

8/159359

Inventors:

Christopher J. Read - Houston TX
Karl M. Guttag - Missouri City TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03M 740

US Classification:

341 65

Abstract:

A data processor Huffman encodes a series of multibit signed digital numbers determining the needed data size by detecting the bit position of the greatest significant bit that differs from the most significant bit. Either a left most bit change detector (237) determines this bit position or a left most one detector (237) determines this bit position from the absolute value of the multibit signed digital number. A set of least significant bits equal in number to the data size are selected from the multibit signed digital number. The data processor formed the Huffman encoded signal by concatenating the data size and the selected least significant bits if the original multibit signed digital number was greater than or equal to zero, or by concatenating the data size with the sum of the selected bits and a multibit digital constant having a number of "1's" equal to the data size. A Huffman encoded string of data is formed by concatenating Huffman encoded signals of the next multibit signed digital number with Huffman encoded signals of prior multibit signed digital numbers in the series. This invention is preferably practiced using a data processing circuit (71) having a three input arithmetic logic unit (230), a status register (210), a barrel rotator (235), either a left most bit change detector or a left most one detector (237) and a mask generator (239).

US Patent:

56734077, Sep 30, 1997

Filed:

Mar 8, 1994

Appl. No.:

8/207987

Inventors:

Sydney W. Poland - Katy TX
Christopher J. Read - Houston TX
Karl M. Guttag - Sugar Land TX
Robert J. Gove - Plano TX
Michael Gill - Plano TX
Nicholas Ing Simmons - Huntingdon, GB2
Erick Oakland - Zavalla TX
Jeremiah E. Golston - Sugar Land TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 930

US Classification:

395375

Abstract:

A data processor includes both integer and floating point operation units and operates as a reduced instruction set computer (RISC). A modification of the normal load/store RISC operations includes within in its instruction set some instructions that permit floating point operations to be paired with load or store operations. These operations include: vector floating point add; vector multiply accumulate; vector floating point multiply; vector multiply subtract; vector reverse subtract; vector round floating point input; vector round integer input; and vector floating point subtract.

US Patent:

54791669, Dec 26, 1995

Filed:

Nov 30, 1993

Appl. No.:

8/160296

Inventors:

Christopher J. Read - Houston TX
Karl M. Guttag - Missouri City TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03M 740

US Classification:

341 65

Abstract:

This invention decodes a continuous stream of Huffman encoded data, each datum having a size portion of a predetermined number of bits and a value portion of a variable number of bits. The invention extracts the size portion, determines the variable number of bits of the value portion and extracts this value portion. The decoding of this value portion differs depending upon the sign bit. If this sign bit is "1", then translation is required. A mask constant having a single "1" bit is rotated an amount equal to the size aligning this single "1" bit with the most significant bit of the value portion. This rotated mask is ANDed with the value portion. A zero result indicates no translation is needed. The translation, if needed, takes place by subtraction. The quantity 2. sup.

US Patent:

55600301, Sep 24, 1996

Filed:

Mar 8, 1994

Appl. No.:

8/208413

Inventors:

Karl M. Guttag - Sugar Land TX
Christopher J. Read - Houston TX
Sydney W. Poland - Katy TX
Robert J. Gove - Plano TX
Jeremiah E. Golston - Sugar Land TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1300

US Classification:

395800

Abstract:

Data processor with a transparency detection data transfer controller. Transparency register stores transparency data. Source address controller calculates source addresses for recall of data to be transferred. A comparator compares recalled data to stored transparency data and indicates whether data to be transferred is to be written to memory. Destination address controller writes data to be transferred into memory at calculated destination addresses if the comparator indicates data to be transferred is to be written to memory. The recalled data is stored in a source register for comparison. In the preferred embodiment data is not written into memory if it matches the transparency data. The transparency register may store a multiple of the minimum amount of data to be transferred. The data to be transferred is organized into data words having a selected size.

US Patent:

56896956, Nov 18, 1997

Filed:

Jun 7, 1995

Appl. No.:

8/482697

Inventors:

Christopher J. Read - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 930

US Classification:

395581

Abstract:

This invention performs conditional operations and conditional branches based upon mixed conditions. The invention performs a first arithmetic/logical operation via an arithmetic logic unit (230). At least one status bit in a status register (210) is set based upon the results. This status bit could be a negative status bit, a carry out status bit, an overflow status bit or a zero status bit. In a first embodiment, the arithmetic logic unit (230) performs a second operation conditional upon a selected one of the status bits. The status bits are then set based upon the results of this second operation. A third operation, which could be an arithmetic logic unit operation, a memory load, memory store, a register to register move, a subroutine call, subroutine return or program branch, is conditional upon the selected status bit, thus performing upon the logical AND of the results of the first and second operations. In a second embodiment, the second operation is conditioned on the inverse of the selected status bit. The result of this second operation also sets the status bits.

US Patent:

54871468, Jan 23, 1996

Filed:

Mar 8, 1994

Appl. No.:

8/209124

Inventors:

Karl M. Guttag - Sugarland TX
Sydney W. Poland - Katy TX
Keith Balmer - Bedford, GB2
Robert J. Gove - Plano TX
Christopher J. Read - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1206

US Classification:

395166

Abstract:

A data processing device includes a memory, a control circuit, a guide table and an address generating circuit. The control circuit receives a packet transfer request and packet transfer parameters. The packet transfer parameters include a start address, dimension values defining a block of addresses, guide table having guide table entries and a table pointer. Each guide table entry has an address value. The table pointer initially points to a first guide table entry in the guide table. The address generating circuit forms a set of a block of addresses for memory access corresponding to each guide table entry, having a start address from a predetermined combination of the start address and the address value of the guide table entry. The block of addresses are formed from the dimension values. Following the memory accesses, the address generating circuit updates the table pointer to point to a next entry in the guide table.

US Patent:

56969546, Dec 9, 1997

Filed:

Jun 7, 1995

Appl. No.:

8/486562

Inventors:

Karl M. Guttag - Sugar Land TX
Keith Balmer - Bedford, GB2
Robert J. Gove - Plano TX
Christopher J. Read - Houston TX
Jeremiah E. Golston - Sugar Land TX
Sydney W. Poland - Katy TX
Nicholas Ing-Simmons - Alconbury Weston, GB2
Philip Moyse - Bronham, GB2

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 1700

US Classification:

395562

Abstract:

A data processing apparatus includes a three input arithmetic logic unit (230) that generates a combination of the three inputs that is selected by a function signal. Data registers (200) store the three data inputs and the arithmetic logic unit output. The second input signal comes from a controllable shifter (235). The shifter could be a left barrel rotator with wrap around or a controllable left/right shifter. The shift amount is a default shift amount stored in a special data register, a predetermined set of bits of data recalled from a data register or zero. A one's constant source (236) is connected to the shifter (235) to supply a multibit digital signal of "1". This permits generating a second input signal of the form 2. sup. N, with N being a left shift amount. The output of the shifter (235) may be stored independently of the arithmetic logic unit (230) result.