Christopher Arden Read

US Patent:

56066775, Feb 25, 1997

Filed:

Jun 7, 1995

Appl. No.:

8/472828

Inventors:

Keith Balmer - Bedford, GB2
Christopher J. Read - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 744

US Classification:

395384

Abstract:

This invention is a method and apparatus for multiplication which enables two factors to be packed into the same size data word as the product. The invention partitions two N bit buses (210, 202) into a first set of M bits and a second set of L bits. In the preferred embodiment the first set of M bits is N/2 most significant bits and the second set of L bits in N/2 least significant bits. Thus N=M+L and M=L. A multiplier (220) multiplies the second sets of L bits of each of the N bit numbers. This results in a product having up to 2L bits. The invention forms an output word having a first set of L bits being the most significant L bits of the product and a second set of M bits being the first set of M bits of the first N bit data word. In the preferred embodiment, a multiplexer (221) selects between the full product of 2L bits and the packed word output. The product may be scaled prior to partitioning via a left shifter (224) which shifts the product a selected number of bit positions.

US Patent:

55128963, Apr 30, 1996

Filed:

Nov 30, 1993

Appl. No.:

8/159359

Inventors:

Christopher J. Read - Houston TX
Karl M. Guttag - Missouri City TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03M 740

US Classification:

341 65

Abstract:

A data processor Huffman encodes a series of multibit signed digital numbers determining the needed data size by detecting the bit position of the greatest significant bit that differs from the most significant bit. Either a left most bit change detector (237) determines this bit position or a left most one detector (237) determines this bit position from the absolute value of the multibit signed digital number. A set of least significant bits equal in number to the data size are selected from the multibit signed digital number. The data processor formed the Huffman encoded signal by concatenating the data size and the selected least significant bits if the original multibit signed digital number was greater than or equal to zero, or by concatenating the data size with the sum of the selected bits and a multibit digital constant having a number of "1's" equal to the data size. A Huffman encoded string of data is formed by concatenating Huffman encoded signals of the next multibit signed digital number with Huffman encoded signals of prior multibit signed digital numbers in the series. This invention is preferably practiced using a data processing circuit (71) having a three input arithmetic logic unit (230), a status register (210), a barrel rotator (235), either a left most bit change detector or a left most one detector (237) and a mask generator (239).

US Patent:

54791669, Dec 26, 1995

Filed:

Nov 30, 1993

Appl. No.:

8/160296

Inventors:

Christopher J. Read - Houston TX
Karl M. Guttag - Missouri City TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H03M 740

US Classification:

341 65

Abstract:

This invention decodes a continuous stream of Huffman encoded data, each datum having a size portion of a predetermined number of bits and a value portion of a variable number of bits. The invention extracts the size portion, determines the variable number of bits of the value portion and extracts this value portion. The decoding of this value portion differs depending upon the sign bit. If this sign bit is "1", then translation is required. A mask constant having a single "1" bit is rotated an amount equal to the size aligning this single "1" bit with the most significant bit of the value portion. This rotated mask is ANDed with the value portion. A zero result indicates no translation is needed. The translation, if needed, takes place by subtraction. The quantity 2. sup.

US Patent:

56896956, Nov 18, 1997

Filed:

Jun 7, 1995

Appl. No.:

8/482697

Inventors:

Christopher J. Read - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 930

US Classification:

395581

Abstract:

This invention performs conditional operations and conditional branches based upon mixed conditions. The invention performs a first arithmetic/logical operation via an arithmetic logic unit (230). At least one status bit in a status register (210) is set based upon the results. This status bit could be a negative status bit, a carry out status bit, an overflow status bit or a zero status bit. In a first embodiment, the arithmetic logic unit (230) performs a second operation conditional upon a selected one of the status bits. The status bits are then set based upon the results of this second operation. A third operation, which could be an arithmetic logic unit operation, a memory load, memory store, a register to register move, a subroutine call, subroutine return or program branch, is conditional upon the selected status bit, thus performing upon the logical AND of the results of the first and second operations. In a second embodiment, the second operation is conditioned on the inverse of the selected status bit. The result of this second operation also sets the status bits.

US Patent:

53272404, Jul 5, 1994

Filed:

Dec 24, 1991

Appl. No.:

7/814970

Inventors:

Jeremiah Golston - SugarLand TX
Christopher J. Read - Houston TX
Walt Bonneau - Missouri City TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

H04N 514
H04N 5213
H04N 701

US Classification:

348607

Abstract:

A method is provided for deinterlacing pixels in a video display system operable to display images as a plurality of pixels arranged in first and second fields of interlaced rows, at least one video component level quantified by a numerical video component value characterizing each pixel in an image with the video component levels for the pixels in the first and second fields being updated on alternate scans. A global mean video component value is computed from the video component values generated for a previous scan of at least one of the first and second fields. A global standard deviation is computed for the global mean. A local mean video component value is computed from the video component values generated for a plurality of pixels being updated as part of the current scan of the first field and defining a neighborhood of a pixel in the second field being deinterlaced. A local standard deviation is computed form the local mean video component value. The local standard deviation is compared with a selective multiple of the global standard deviation and if the local standard deviation is less than the selected multiple of the global standard deviation, the video component value generated for the pixel being deinterlaced as part of the previous scan of the second field is carried forward and if the local standard deviation exceeds the selected multiple of the global standard deviation then the video component value for the pixel being deinterlaced is set to the computed local mean video component value.

US Patent:

54208092, May 30, 1995

Filed:

Nov 30, 1993

Appl. No.:

8/160116

Inventors:

Christopher J. Read - Houston TX
Karl M. Guttag - Missouri City TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G06F 700
G06F 738

US Classification:

36471501

Abstract:

A method of computing a mean squared error between a predetermined plural number of pairs of first and second values employs a data processing apparatus (71, 72, 73, 74) having data registers (200), an arithmetic logic unit (230), a flags register (211), a multiplication unit (220), a source of instructions and an instruction decoder (245, 246, 250). The arithmetic logic unit (230) forms a difference between pairs. A status detector determines whether the result is less than zero. The flags register (211) stores status bits indicating this detected status. The arithmetic logic unit (230) conditionally either adds the difference to zero if the status bit indicates the difference was not less than zero or subtracts the difference from zero if the status bit indicated the difference was less than zero. The multiplication unit (220) forms the square. The square is added to a running sum.

US Patent:

52724689, Dec 21, 1993

Filed:

Apr 30, 1991

Appl. No.:

7/693506

Inventors:

Christopher J. Read - Houston TX

Assignee:

Texas Instruments Incorporated - Dallas TX

International Classification:

G09G 128

US Classification:

345153

Abstract:

A colorspace converter for use with image processing systems. The colorspace converter transforms digitized image data in one colorspace into image data in another colorspace, for use by a computer monitor. The colorspace converter uses look-up tables and other logic devices, and avoids the need for processor intervention. The look-up tables may be loaded for simple mapping, and extension look-up tables may be loaded for nonlinear extension transformations.