Christopher Allen Russell

US Patent:

20220413859, Dec 29, 2022

Filed:

Jun 25, 2021

Appl. No.:

17/358082

Inventors:

- Santa Clara CA, US
Jason W. Brandt - Austin TX, US
H. Peter Anvin - San Jose CA, US
Christopher M. Russell - Austin TX, US
Gilbert Neiger - Portland OR, US

International Classification:

G06F 9/30
G06F 9/455
G06F 9/48

Abstract:

In one embodiment, a processor includes: a front end circuit to fetch and decode a read list instruction, the read list instruction to cause storage to a memory of a software-provided list of processor state information; and an execution circuit coupled to the front end circuit. The execution circuit, in response to the decoded read list instruction, is to read the processor state information stored in the processor and store each datum of the processor state information into an entry of a data table in the memory. Other embodiments are described and claimed.

US Patent:

20230056699, Feb 23, 2023

Filed:

Aug 23, 2021

Appl. No.:

17/409090

Inventors:

- Santa Clara CA, US
Christopher Russell - Austin TX, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 15/78
G06F 9/38

Abstract:

Methods and apparatus relating to loop driven region based frontend translation control for performant and secure data-space guided micro-sequencing are described. In an embodiment, Data-space Translation Logic (DTL) circuitry receives a static input and a dynamic input and generates one or more outputs based at least in part on the static input and the dynamic input. A frontend counter generates a count value for the dynamic input based at least in part on an incremented/decremented counter value and a next counter value from the DTL circuitry. The DTL circuitry is capable to receive a new dynamic input prior to consumption of the one or more outputs. Other embodiments are also disclosed and claimed.

US Patent:

20230057623, Feb 23, 2023

Filed:

Aug 23, 2021

Appl. No.:

17/409062

Inventors:

- Santa Clara CA, US
Christopher Russell - Austin TX, US

Assignee:

Intel Corporation - Santa Clara CA

International Classification:

G06F 15/78
G06F 9/38

Abstract:

Methods and apparatus relating to issue, execution, and backend driven frontend translation control for performant and secure data-space guided micro-sequencing are described. In an embodiment, Data-space Translation Logic (DTL) circuitry receives a static input and a dynamic input, and generates one or more outputs based at least in part on the static input and the dynamic input. The DTL circuitry generates the one or more outputs prior to commencement of speculation operations in a processor. Other embodiments are also disclosed and claimed.