Christopher C Schell

age ~58

from Wasilla, AK

Also known as:
  • Christopher C Shell
  • Cc Schell
  • Schell Cc

Christopher Schell Phones & Addresses

  • Wasilla, AK
  • Gold Bar, WA
  • Redmond, WA
  • Covington, WA
  • Puyallup, WA
  • Seatac, WA
  • Kiona, WA

Work

  • Company:
    Davis Polk & Wardwell LLP
  • Address:

Specialities

Corporate & Incorporation • Capital Markets • Capital Markets

Us Patents

  • Apparatus And Method To Hold Pll Output Frequency When Input Clock Is Lost

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  • US Patent:
    20120280735, Nov 8, 2012
  • Filed:
    May 2, 2011
  • Appl. No.:
    13/099253
  • Inventors:
    Tom Christiansen - Federal Way WA, US
    Christopher Andrew Schell - Tacoma WA, US
  • Assignee:
    National Semiconductor Corporation - Santa Clara CA
  • International Classification:
    H03K 12/00
  • US Classification:
    327184
  • Abstract:
    A clock conditioning circuit including a phase detector circuit configured to provide an analog tuning signal indicative of a phase relationship between a reference clock to be conditioned and a generated clock. The controlled oscillator is configured to produce the generated clock, with the generated clock having an output frequency adjustable in response to an analog tuning signal applied to a control signal input of the controlled oscillator. Converter circuitry is provided to produce a digital representation of the analog tuning signal when the mode control circuitry is in a tracking mode. In the event the reference clock is lost, the mode control circuitry switches to a holdover mode so as to provide an analog holdover signal to the control signal input based upon the digital representations produced just prior to the loss of the reference clock.
  • Phase Cancellation In A Phase-Locked Loop

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  • US Patent:
    20200321969, Oct 8, 2020
  • Filed:
    Jun 23, 2020
  • Appl. No.:
    16/908786
  • Inventors:
    - Dallas TX, US
    Christopher Andrew SCHELL - Tacoma WA, US
    Arvind SRIDHAR - Issaquah WA, US
    Sinjeet Dhanvantray PAREKH - San Jose CA, US
  • International Classification:
    H03L 7/093
    H03L 7/14
    H03L 7/087
    H03L 7/083
  • Abstract:
    A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.
  • Cycle Slip Detection And Correction In Phase-Locked Loop

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  • US Patent:
    20200177192, Jun 4, 2020
  • Filed:
    Feb 4, 2020
  • Appl. No.:
    16/780957
  • Inventors:
    - Dallas TX, US
    Christopher Andrew SCHELL - Tacoma WA, US
    Sinjeet Dhanvantray PAREKH - San Jose CA, US
  • International Classification:
    H03L 7/099
    H03L 7/083
    H03L 7/093
    G04F 10/00
  • Abstract:
    A digital phase-locked loop (DPLL) includes a voltage-controlled oscillator to generate an output clock, a filter coupled to the voltage-controlled oscillator, and a time-to-digital converter (TDC) that receives a reference clock and a feedback clock. The feedback clock is derived from the output clock. The TDC generates a digital output value. The DPLL also includes a cycle slip detector circuit coupled to the TDC. The cycle slip detector circuit detects a cycle slip based on the digital output value and adjusts the digital output value by a second digital value that corresponds to an integer multiple of a period of the reference clock.
  • Phase Cancellation In A Phase-Locked Loop

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  • US Patent:
    20200021301, Jan 16, 2020
  • Filed:
    Sep 25, 2019
  • Appl. No.:
    16/582341
  • Inventors:
    - Dallas TX, US
    Christopher Andrew SCHELL - Tacoma WA, US
    Arvind SRIDHAR - Issaquah WA, US
    Sinjeet Dhanvantray PAREKH - San Jose CA, US
  • International Classification:
    H03L 7/093
    H03L 7/083
    H03L 7/087
    H03L 7/14
  • Abstract:
    A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.
  • Digital Phase-Locked Loop

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  • US Patent:
    20190348989, Nov 14, 2019
  • Filed:
    Aug 10, 2018
  • Appl. No.:
    16/101009
  • Inventors:
    - Dallas TX, US
    Christopher Andrew SCHELL - Tacoma WA, US
    Henry YAO - Santa Clara CA, US
    Raghu GANESAN - Bengaluru, IN
  • International Classification:
    H03L 7/099
    H03L 7/083
    H03L 7/091
    H03L 7/18
    H03L 7/10
    G04F 10/00
  • Abstract:
    A phase-locked loop circuit includes a first time-to-digital converter (TDC) to receive an input reference signal, a digital-controlled oscillator (DCO), and a first divider coupled to an output of the DCO. The first divider divides down a frequency of an output from the DCO. A second divider divides down a frequency of an output form the first divider to provide a second divider output to an input of the first TDC. The first TDC generates an output digital value encoding a time difference between corresponding edges of the input reference signal and the second divider output. A second TDC receives the input reference signal. An averager circuit generates a digital output that is indicative of an average of an output from the second TDC. A subtractor circuit subtracts the digital output from the average and the output digital value from the first TDC.
  • Switch Between Input Reference Clocks Of Different Frequencies In A Phase Locked Loop (Pll) Without Phase Impact

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  • US Patent:
    20190288694, Sep 19, 2019
  • Filed:
    Dec 20, 2018
  • Appl. No.:
    16/226938
  • Inventors:
    - Dallas TX, US
    Eric Paul LINDGREN - Bonney Lake WA, US
    Christopher Andrew SCHELL - Tacoma WA, US
  • International Classification:
    H03L 7/07
    H03K 5/13
    H03L 7/093
  • Abstract:
    A phase-locked loop (PLL) includes a selection circuit including a plurality of inputs, each input to receive a separate reference clock. A programmable reference clock divider divides down the reference clock selected by the selection circuit to generate a divided down reference clock. A feedback clock divider divides down an output clock from the PLL to generate a feedback clock. A time-to-digital converter (TDC) generates a digital output value based on a phase difference between the divided down reference clock and the feedback clock. A circuit including a finite state machine, causes, responsive to an indication to change reference clocks, the reference clock divider and the feedback clock divider to be held in a reset state, the divide ratio of the reference clock divider to be modified, and then to release the reset state.
  • Crystal Oscillator Offset Trim In A Phase-Locked Loop

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  • US Patent:
    20190288699, Sep 19, 2019
  • Filed:
    Dec 20, 2018
  • Appl. No.:
    16/227777
  • Inventors:
    - Dallas TX, US
    Christopher Andrew SCHELL - Tacoma WA, US
    Arvind SRIDHAR - Issaquah WA, US
  • International Classification:
    H03L 7/099
    H03L 7/093
  • Abstract:
    A phase-locked loop (PLL) includes a time-to-digital converter (TDC) to receive a reference clock. The PLL also includes a digital loop filter coupled to the TDC. The digital loop filter repeatedly generates frequency control words. An analog phase-locked loop (APLL) includes a programmable frequency divider. A non-volatile memory device stores a value from the digital loop filter. The PLL includes a free-run control circuit. Upon a power-on reset process, the free-run circuit retrieves the value from the non-volatile memory to adjust a divide ratio of the programmable frequency divider based on the retrieved value. Upon a reference clock provided to the TDC, the free-run control circuit continues to adjust the divide ratio of the programmable frequency divider based on both the retrieved value from the non-volatile memory and a current frequency control word from the digital loop filter.
  • Phase Cancellation In A Phase-Locked Loop

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  • US Patent:
    20190280699, Sep 12, 2019
  • Filed:
    Dec 27, 2018
  • Appl. No.:
    16/233283
  • Inventors:
    - Dallas TX, US
    Christopher Andrew SCHELL - Tacoma WA, US
    Arvind SRIDHAR - Issaquah WA, US
    Sinjeet Dhanvantray PAREKH - San Jose CA, US
  • International Classification:
    H03L 7/093
    H03L 7/083
    H03L 7/087
    H03L 7/14
  • Abstract:
    A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.

Lawyers & Attorneys

Christopher Schell Photo 1

Christopher Schell - Lawyer

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Office:
Davis Polk & Wardwell LLP
Specialties:
Corporate & Incorporation
Capital Markets
Capital Markets
ISLN:
914841836
Admitted:
1999
University:
Yale University, B.A., 1993
Law School:
Yale University Law School, J.D., 1998

Resumes

Christopher Schell Photo 2

Christopher Schell

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Christopher Schell Photo 3

Christopher Schell

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Christopher Schell Photo 4

Christopher Schell

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Christopher Schell Photo 5

Christopher Schell

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Location:
United States
Christopher Schell Photo 6

Christopher Schell

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Location:
United States
Christopher Schell Photo 7

Christopher Schell

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Location:
United States

Flickr

Youtube

Science Stories: Urban EcologistChristo... ...

Christopher Schell, Assistant Professor of Urban Ecology at University...

  • Duration:
    6m 40s

Dr. Christopher J. Schell--09-21-22

Dr. Christopher J. Schell, Department of Environmental Science, Policy...

  • Duration:
    1h 4m 37s

What Does It Mean To Make A Company "Just"? o...

Christophe shell um i see your video is on uh there's your slide but w...

  • Duration:
    20m 34s

15 for 15 ~ Chris Schell

Project Exploration celebrates 15 years with 15 interviews of extraord...

  • Duration:
    5m 7s

Black in STEM 2022: Dr. Chris Schell

As part of the Field Museum's 2022 Black History Month programming, Dr...

  • Duration:
    1h 24s

Science Seminar: Living for the city - Dr. Ch...

Living for the city: Exploring the convergence of wildlife, society, h...

  • Duration:
    1h 4s

Classmates

Christopher Schell Photo 16

Christopher Schell

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Schools:
Long Hill Elementary School Shelton CT 1998-2002, West Shore Middle School Milford CT 2001-2004
Community:
Kristy Provost
Christopher Schell Photo 17

Christopher Schell

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Schools:
Canaan Elementary School Patchogue NY 1979-1983
Community:
Melleny Fox
Christopher Schell Photo 18

Christopher Schell | St. ...

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Christopher Schell Photo 19

Chris Schell, University ...

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Christopher Schell Photo 20

Chris Schell, Baker High ...

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Christopher Schell Photo 21

Canaan Elementary School,...

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Graduates:
Stephanie Chatman (1974-1978),
Christopher Schell (1979-1983),
Jenean Onorato (1977-1981),
John Long (1993-2002),
George Trocchiano (1973-1975)
Christopher Schell Photo 22

Brock District High Schoo...

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Graduates:
Christopher Schell (1992-1996),
Ross Drew (1950-1954),
Robert Sheppard (1998-2002),
Marie Nicholls (1975-1979)
Christopher Schell Photo 23

Western Reserve High Scho...

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Graduates:
Chris Montgomery (1987-1991),
Debbie Nestor (1965-1969),
Christopher Barker (1988-1992),
Chris Schell (1972-1976)

Facebook

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Christopher Schell

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Christopher Schell Photo 25

Christopher Schell

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Christopher Schell Photo 26

Christopher Schell

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Christopher Schell Photo 27

Chris Schell

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Christopher Schell Photo 28

Christopher Schell

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Christopher Schell Photo 29

Christopher Schell

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Christopher Schell Photo 30

Christopher A. Schell

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Christopher Schell Photo 31

Christopher Schell

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Googleplus

Christopher Schell Photo 32

Christopher Schell

Education:
Pfalzwerke AG - Energieelektroniker/Anlagentechnik
Christopher Schell Photo 33

Christopher Schell

Myspace

Christopher Schell Photo 34

christopher schell

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Locality:
MILFORD, CONNECTICUT
Gender:
Male
Birthday:
1948
Christopher Schell Photo 35

Christopher Schell

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Locality:
PORT SAINT JOE, Florida
Gender:
Male
Birthday:
1949
Christopher Schell Photo 36

Christopher Schell

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Locality:
Saalfelden, Salzburg
Gender:
Male
Birthday:
1948
Christopher Schell Photo 37

CHRISTOPHER schell

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Locality:
TERRE HAUTE, Indiana
Gender:
Male
Birthday:
1943

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