Tom Christiansen - Federal Way WA, US Christopher Andrew Schell - Tacoma WA, US
Assignee:
National Semiconductor Corporation - Santa Clara CA
International Classification:
H03K 12/00
US Classification:
327184
Abstract:
A clock conditioning circuit including a phase detector circuit configured to provide an analog tuning signal indicative of a phase relationship between a reference clock to be conditioned and a generated clock. The controlled oscillator is configured to produce the generated clock, with the generated clock having an output frequency adjustable in response to an analog tuning signal applied to a control signal input of the controlled oscillator. Converter circuitry is provided to produce a digital representation of the analog tuning signal when the mode control circuitry is in a tracking mode. In the event the reference clock is lost, the mode control circuitry switches to a holdover mode so as to provide an analog holdover signal to the control signal input based upon the digital representations produced just prior to the loss of the reference clock.
- Dallas TX, US Christopher Andrew SCHELL - Tacoma WA, US Arvind SRIDHAR - Issaquah WA, US Sinjeet Dhanvantray PAREKH - San Jose CA, US
International Classification:
H03L 7/093 H03L 7/14 H03L 7/087 H03L 7/083
Abstract:
A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.
Cycle Slip Detection And Correction In Phase-Locked Loop
- Dallas TX, US Christopher Andrew SCHELL - Tacoma WA, US Sinjeet Dhanvantray PAREKH - San Jose CA, US
International Classification:
H03L 7/099 H03L 7/083 H03L 7/093 G04F 10/00
Abstract:
A digital phase-locked loop (DPLL) includes a voltage-controlled oscillator to generate an output clock, a filter coupled to the voltage-controlled oscillator, and a time-to-digital converter (TDC) that receives a reference clock and a feedback clock. The feedback clock is derived from the output clock. The TDC generates a digital output value. The DPLL also includes a cycle slip detector circuit coupled to the TDC. The cycle slip detector circuit detects a cycle slip based on the digital output value and adjusts the digital output value by a second digital value that corresponds to an integer multiple of a period of the reference clock.
- Dallas TX, US Christopher Andrew SCHELL - Tacoma WA, US Arvind SRIDHAR - Issaquah WA, US Sinjeet Dhanvantray PAREKH - San Jose CA, US
International Classification:
H03L 7/093 H03L 7/083 H03L 7/087 H03L 7/14
Abstract:
A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.
A phase-locked loop circuit includes a first time-to-digital converter (TDC) to receive an input reference signal, a digital-controlled oscillator (DCO), and a first divider coupled to an output of the DCO. The first divider divides down a frequency of an output from the DCO. A second divider divides down a frequency of an output form the first divider to provide a second divider output to an input of the first TDC. The first TDC generates an output digital value encoding a time difference between corresponding edges of the input reference signal and the second divider output. A second TDC receives the input reference signal. An averager circuit generates a digital output that is indicative of an average of an output from the second TDC. A subtractor circuit subtracts the digital output from the average and the output digital value from the first TDC.
Switch Between Input Reference Clocks Of Different Frequencies In A Phase Locked Loop (Pll) Without Phase Impact
- Dallas TX, US Eric Paul LINDGREN - Bonney Lake WA, US Christopher Andrew SCHELL - Tacoma WA, US
International Classification:
H03L 7/07 H03K 5/13 H03L 7/093
Abstract:
A phase-locked loop (PLL) includes a selection circuit including a plurality of inputs, each input to receive a separate reference clock. A programmable reference clock divider divides down the reference clock selected by the selection circuit to generate a divided down reference clock. A feedback clock divider divides down an output clock from the PLL to generate a feedback clock. A time-to-digital converter (TDC) generates a digital output value based on a phase difference between the divided down reference clock and the feedback clock. A circuit including a finite state machine, causes, responsive to an indication to change reference clocks, the reference clock divider and the feedback clock divider to be held in a reset state, the divide ratio of the reference clock divider to be modified, and then to release the reset state.
Crystal Oscillator Offset Trim In A Phase-Locked Loop
- Dallas TX, US Christopher Andrew SCHELL - Tacoma WA, US Arvind SRIDHAR - Issaquah WA, US
International Classification:
H03L 7/099 H03L 7/093
Abstract:
A phase-locked loop (PLL) includes a time-to-digital converter (TDC) to receive a reference clock. The PLL also includes a digital loop filter coupled to the TDC. The digital loop filter repeatedly generates frequency control words. An analog phase-locked loop (APLL) includes a programmable frequency divider. A non-volatile memory device stores a value from the digital loop filter. The PLL includes a free-run control circuit. Upon a power-on reset process, the free-run circuit retrieves the value from the non-volatile memory to adjust a divide ratio of the programmable frequency divider based on the retrieved value. Upon a reference clock provided to the TDC, the free-run control circuit continues to adjust the divide ratio of the programmable frequency divider based on both the retrieved value from the non-volatile memory and a current frequency control word from the digital loop filter.
- Dallas TX, US Christopher Andrew SCHELL - Tacoma WA, US Arvind SRIDHAR - Issaquah WA, US Sinjeet Dhanvantray PAREKH - San Jose CA, US
International Classification:
H03L 7/093 H03L 7/083 H03L 7/087 H03L 7/14
Abstract:
A phase-locked loop (PLL) including a multiplexer with multiple inputs, each input coupled to receive a different reference clock. A time-to-digital converter (TDC) generates a TDC output value based on a phase difference between a reference clock from the multiplexer and a feedback clock. An averager circuit coupled to an output of the TDC. An adder circuit is coupled to outputs of the TDC and the averager circuit. A loop filter is coupled to an output of the adder circuit.