Christopher A Spencer

US Patent:

7523321, Apr 21, 2009

Filed:

Jan 16, 2004

Appl. No.:

10/759639

Inventors:

Ayedin Nikazm - Austin TX, US
Christopher A. Spencer - Austin TX, US

Assignee:

Dell Products L.P. - Round Rock TX

International Classification:

H02J 3/46
H02J 1/00

US Classification:

713300, 713310, 713320, 713321, 713322, 713323, 713324, 713330, 713340, 323282, 307 80, 307 81

Abstract:

An information handling system (IHS) includes a system board including a processor, a first battery for supplying power to the system board, a second battery for supplying power to the system board, and a switching circuit. The switching circuit is configured to repeatedly switch between the first battery and the second battery for supplying power to the system board to provide more power to the IHS than is possible if only one battery were continuously providing power to the IHS.

US Patent:

8151135, Apr 3, 2012

Filed:

Apr 22, 2010

Appl. No.:

12/765302

Inventors:

Thomas L. Pratt - Austin TX, US
Christopher A. Spencer - Austin TX, US
Munif M. Farhan - Round Rock TX, US
Sharon Lyn Hanson - Austin TX, US

Assignee:

Dell Products L.P. - Round Rock TX

International Classification:

G06F 11/00

US Classification:

714 51, 714 63

Abstract:

Systems and methods for reducing problems and disadvantages associated with traditional approaches to data and program storage on an information handling system are provided. A method may include determining if a primary storage resource has a failure. The method may further include, in response to determining that the storage resource does not have a failure: booting from a first operating system stored on the primary storage resource, monitoring data stored to the primary storage resource to identify data to be copied to a persistent storage resource, and copying the identified data to the persistent storage resource. The method may further include, in response to determining that the storage resource has a failure: booting from a second operating system stored on the persistent storage resource, and via the second operating system, providing access to the copied identified data copied to the persistent storage resource.

US Patent:

20120059866, Mar 8, 2012

Filed:

Sep 3, 2010

Appl. No.:

12/875757

Inventors:

James Conyngham - Austin TX, US
Jeffrey T. Brady - Orlando FL, US
Christopher L. Spencer - Oviedo FL, US

Assignee:

ADVANCED MICRO DEVICES, INC. - Sunnyvale CA

International Classification:

G06F 7/44
G06F 7/42

US Classification:

708503, 708504, 708505

Abstract:

A method and apparatus provides for performing floating-point division using input check/output correction floating-point division logic and a floating-point division fix-up instruction (e.g., an instruction, command, signal or other indicator). In one example, the apparatus includes a processor having a floating-point arithmetic logic unit (ALU) that includes the input check/output correction floating-point division logic. The input check/output correction floating-point division logic is responsive to the floating-point division fix-up instruction executable by the floating-point ALU that causes the input check/output correction floating-point division logic to examine a first input representing a numerator and a second input representing a denominator to determine whether a special case of floating-point division occurs. The floating-point division fix-up instruction also causes the input check/output correction floating-point division logic to provide an output representing a floating-point division result based on the determined special case of floating-point division and a third input representing a candidate quotient.

US Patent:

20210248006, Aug 12, 2021

Filed:

Apr 26, 2021

Appl. No.:

17/240406

Inventors:

- Cupertino CA, US
Dimitri Tan - Austin TX, US
Christopher L. Spencer - Chuluota FL, US
Jeffrey T. Brady - Orlando FL, US
Ralph C. Taylor - Orlando FL, US
Terence M. Potter - Austin TX, US

International Classification:

G06F 9/50

Abstract:

In various embodiments, a resource allocation management circuit may allocate a plurality of different types of hardware resources (e.g., different types of registers) to a plurality of threads. The different types of hardware resources may correspond to a plurality of hardware resource allocation circuits. The resource allocation management circuit may track allocation of the hardware resources to the threads using state identification values of the threads. In response to determining that fewer than a respective requested number of one or more types of the hardware resources are available, the resource allocation management circuit may identify one or more threads for deallocation. As a result, the hardware resource allocation system may allocate hardware resources to threads more efficiently (e.g., may deallocate hardware resources allocated to fewer threads), as compared to a hardware resource allocation system that does not track allocation of hardware resources to threads using state identification values.

US Patent:

20190042312, Feb 7, 2019

Filed:

Aug 4, 2017

Appl. No.:

15/669445

Inventors:

- Cupertino CA, US
Dimitri Tan - Austin TX, US
Christopher L. Spencer - Chuluota FL, US
Jeffrey T. Brady - Orlando FL, US
Ralph C. Taylor - Orlando FL, US
Terence M. Potter - Austin TX, US

International Classification:

G06F 9/50

Abstract:

In various embodiments, a resource allocation management circuit may allocate a plurality of different types of hardware resources (e.g., different types of registers) to a plurality of threads. The different types of hardware resources may correspond to a plurality of hardware resource allocation circuits. The resource allocation management circuit may track allocation of the hardware resources to the threads using state identification values of the threads. In response to determining that fewer than a respective requested number of one or more types of the hardware resources are available, the resource allocation management circuit may identify one or more threads for deallocation. As a result, the hardware resource allocation system may allocate hardware resources to threads more efficiently (e.g., may deallocate hardware resources allocated to fewer threads), as compared to a hardware resource allocation system that does not track allocation of hardware resources to threads using state identification values.