Christopher R Weaver

US Patent:

20110153990, Jun 23, 2011

Filed:

Dec 23, 2009

Appl. No.:

12/646762

Inventors:

Guilherme D. Ottoni - Cambell CA, US
Hong Wang - Santa Clara CA, US
Christopher T. Weaver - Austin TX, US
Thomas A. Hartin - Austin TX, US
Wei Li - Santa Clara CA, US
Jason W. Brandt - Austin TX, US

International Classification:

G06F 9/30
G06F 9/38

US Classification:

712208, 712225, 712234, 712E09016, 712E09045

Abstract:

An apparatus is described having decode circuitry to decode a first instruction, wherein the first instruction indicates that a copy of a plurality of condition codes bits is to be copied from a first register to a second register. The apparatus also has first execution circuitry to copy a plurality of condition code bits from a first register to a second register.

US Patent:

20230095622, Mar 30, 2023

Filed:

Sep 24, 2021

Appl. No.:

17/485194

Inventors:

- Santa Clara CA, US
Indrani Paul - Austin TX, US
Benjamin Tsien - Santa Clara CA, US
Christopher T. Weaver - Boxborough MA, US
John P. Petry - San Diego CA, US
Mihir Shaileshbhai Doctor - Santa Clara CA, US
Thomas J. Gibney - Boxborough MA, US

Assignee:

Advanced Micro Devices, Inc. - Santa Clara CA

International Classification:

G06F 1/26
G06F 13/40

Abstract:

A method and apparatus for isolating and restoring general-purpose input/output (GPIO) pads in a computer system includes identifying GPIO pads associated with the region responsive to an entry into a power-down state of a region of a circuit. The GPIO pads are isolated from one or more external circuits. Upon exit from the power-down state, each associated GPIO pad is restored to a current value.

US Patent:

20230031388, Feb 2, 2023

Filed:

Jul 30, 2021

Appl. No.:

17/390429

Inventors:

- Santa Clara CA, US
Indrani Paul - Austin TX, US
Alexander J. Branover - Boxborough MA, US
Thomas J. Gibney - Boxborough MA, US
Mihir Shaileshbhai Doctor - Santa Clara CA, US
John P. Petry - Santa Clara CA, US
Stephen V. Kosonocky - Fort Collins CO, US
Christopher T. Weaver - Boxborough MA, US

Assignee:

Advanced Micro Devices, Inc. - Santa Clara CA

International Classification:

G06F 1/3203

Abstract:

Systems, methods, and devices for integrated circuit power management. A mode of a power management state is entered, from the power management state, in response to an entry condition of the mode. A device that is otherwise powered off in the power management state is powered on in the mode of the power management state. In some implementations, the device includes a communications path between a second device and a third device. In some implementations, the device is in a power domain that is powered off in the power management state. In some implementations, the power domain is powered off in the mode. In some implementations, the device is powered on in the mode via a power rail that is specific to the mode. In some implementations, the entry condition of the mode includes an amount of data stored for display in a display buffer falling below a threshold amount.