Chun C Chan

US Patent:

6425114, Jul 23, 2002

Filed:

Jan 31, 2000

Appl. No.:

09/494605

Inventors:

Chun Chan - Sunnyvale CA
Bing Yi - Sunnyvale CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 1750

US Classification:

716 6, 716 5

Abstract:

Skew is reduced in a tree-shaped distribution network having plural levels and plural nodes at each level, where a node at one level connects to plural nodes at the next lower level. Initially, the current level is set to the bottom level of the network. Delay ranges are then obtained corresponding to nodes at the current level and the delay ranges are shifted in an attempt to align delay ranges corresponding to nodes at the current level that connect to the same node at the next higher level. These steps are then repeated for all levels in order from the bottom level to the top level.

US Patent:

6480989, Nov 12, 2002

Filed:

Jun 29, 1998

Appl. No.:

09/106890

Inventors:

Chun Chan - San Jose CA
Tammy Huang - Fremont CA
Mike Liang - Milpitas CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 1750

US Classification:

716 8, 257211, 716 11, 716 14

Abstract:

Provided is a technique for designing an integrated circuit die which includes a semiconductor layer, a primary metal layer, a horizontal metal layer and a vertical metal layer. Electronic components are laid out on the semiconductor layer, and a primary power distribution network for distributing power to the electronic components is laid out on the primary metal layer. Then, a uniform trunk width is calculated for all trunks in a power mesh based on a desired maximum voltage drop for the generated electronic component layout. Finally, horizontal power trunks are laid out on the horizontal metal layer and vertical power trunks are laid out on the vertical metal layer using the calculated uniform trunk width, so as to form the power mesh, and an electrical connection is specified between the power mesh and the primary power distribution network.

US Patent:

6492736, Dec 10, 2002

Filed:

Mar 14, 2001

Appl. No.:

09/808441

Inventors:

Chun Chan - Sunnyvale CA
Bo Shen - Fremont CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2348

US Classification:

257773, 257750, 257758, 257920

Abstract:

A multiple layer mesh design that provides that a bridge associated with a second layer connects a rail on a first layer to a trunk on a fourth layer. If the trunk on the third layer shadows a plurality of rails on the first layer, preferably the bridge is at least as wide as a sum of the widths of the rails on the first layer which are shadowed by the trunk on the third layer. If the trunk on the third layer shadows a single rail on the first layer, preferably the bridge is at least as wide as twice the width of the rail on the first layer.

US Patent:

7207021, Apr 17, 2007

Filed:

Jan 14, 2005

Appl. No.:

11/036822

Inventors:

Qian Cui - San Jose CA, US
Chun Chan - Sunnyvale CA, US

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

G06F 17/50

US Classification:

716 6, 703 14, 716 1

Abstract:

A method is provided for selecting a frequency-based ramptime limit for a technology. The method includes creating a logic chain with cells from the technology and applying a sequence of signals to the logic chain. Each signal has a different ramptime relative to a clock period. At least one signal quality characteristic is measured along the logic chain for each of the signals. The frequency-based ramptime limit is selected based on a comparison of the measured signal quality characteristics measured to at least one predefined signal quality value.

US Patent:

53650700, Nov 15, 1994

Filed:

Apr 29, 1992

Appl. No.:

7/875778

Inventors:

Oscar A. Anderson - Berkeley CA
Chun F. Chan - Hayward CA
Ka-Ngo Leung - Hercules CA

Assignee:

The Regents of the University of California - Oakland CA

International Classification:

H01J 2702

US Classification:

250423R

Abstract:

A negative ion source is constructed to produce H. sup. - ions without using Cesium. A high percentage of secondary electrons that typically accompany the extracted H. sup. - are trapped and eliminated from the beam by permanent magnets in the initial stage of acceleration. Penetration of the magnetic field from the permanent magnets into the ion source is minimized. This reduces the destructive effect the magnetic field could have on negative ion production and extraction from the source. A beam expansion section in the extractor results in a strongly converged final beam.

US Patent:

63235595, Nov 27, 2001

Filed:

Jun 23, 1998

Appl. No.:

9/103654

Inventors:

Chun Chan - San Jose CA
Mike Liang - Milpitas CA

Assignee:

LSI Logic Corporation - Milpitas CA

International Classification:

H01L 2348

US Classification:

257778

Abstract:

A flip-chip integrated circuit die includes a semiconductor substrate, electronic components implemented on the semiconductor substrate, several plural metal layers, wires routed between the electronic components on the metal layers, a top layer, and bump pads arranged in a hexagonal array on the top layer. According to another aspect, the invention is directed to flip-chip integrated circuit design, in which a circuit description is input and standardized cells which correspond to electronic components in the circuit description are obtained. The standardized cells are laid out on the surface of the die using a rectangular-based layout technique, and bump pads are laid out in a hexagonal array.

US Patent:

20210093106, Apr 1, 2021

Filed:

Sep 23, 2020

Appl. No.:

17/029958

Inventors:

- Burlingame CA, US
Chun Leung Chan - San Francisco CA, US

International Classification:

A47G 9/10
A47G 9/02

Abstract:

A pillow component includes a material layer having a top layer, a bottom layer and one or more sides separating the top layer from the bottom layer, and an interior spaced defined between the top layer and the bottom layer, the interior space configured to receive a filler. The material layer is formed by seamless knitting and is seamless about an entirety of a periphery extending in a first direction around the top layer, the bottom layer and the one or more sides. The characteristics of the knit material layer or fabric can be widely varied. A pillow includes the pillow component and a filler in the interior space.

US Patent:

20180325291, Nov 15, 2018

Filed:

Oct 4, 2017

Appl. No.:

15/724982

Inventors:

- Burlingame CA, US
Chun Leung Chan - San Francisco CA, US
Jing Chen - Cupertino CA, US

International Classification:

A47G 9/02
A47G 9/10
A47G 9/04

Abstract:

An expandable pillow cover includes a first layer and a second layer positioned opposite first layer to define an interior space therebetween. The first and second layers are joined to one another at at least junctures of at least two opposing openable sides, and at least two other sides, the at least two opposing openable sides being between the two other sides, wherein the openable sides and the other sides define four corners at which the first and second layers are joined to one another. Gusset panels are positioned between the first layer and the second layer in the interior space and adjacent the at least two opposing openable sides. At least two fasteners, one at each of the at least two opposing openable sides movable independently of each other between an open condition and a closed condition. The cover is adjustable between a first condition where one or both of the fasteners are fastened to contract its respective gusset panel and the interior space has a first volume, and a second condition where one or both of the fasteners are unfastened to expand its respective gusset panel and the interior space has a second volume greater than the first volume.