Chun C Chen

US Patent:

6922109, Jul 26, 2005

Filed:

Apr 25, 2002

Appl. No.:

10/131034

Inventors:

Siavash Fallahi - Newport Coast CA, US
Chun Ying Chen - Irvine CA, US
Mark J. Chambers - Mission Viejo CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03L007/00

US Classification:

331 2, 331 25

Abstract:

A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.

US Patent:

7116176, Oct 3, 2006

Filed:

Jun 15, 2004

Appl. No.:

10/866754

Inventors:

Siavash Fallahi - Newport Coast CA, US
Chun Ying Chen - Irvine CA, US
Mark J. Chambers - Mission Viejo CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03L 7/00

US Classification:

331 2, 331 25

Abstract:

A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.

US Patent:

7274260, Sep 25, 2007

Filed:

Aug 1, 2006

Appl. No.:

11/496421

Inventors:

Siavash Fallahi - Newport Coast CA, US
Chun Ying Chen - Irvine CA, US
Mark J. Chambers - Mission Viejo CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03L 7/00

US Classification:

331 2, 331 57

Abstract:

A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.

US Patent:

7379520, May 27, 2008

Filed:

Apr 25, 2002

Appl. No.:

10/131033

Inventors:

Chun Ying Chen - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H04L 7/00

US Classification:

375371, 375354

Abstract:

A phase rotator generates an output signal having plurality of possible output phases with reduced phase jitter. The low jitter phase rotator includes a plurality of differential amplifiers configured to receive a plurality of input differential signals having different phases, and configured to generate a plurality of weighted signals responsive to the plurality of input differential signals. A plurality of digital-to-analog converters (DAC) are arranged into a plurality of groups, each group of DACs configured to provide current for one of the corresponding differential amplifiers. The number of active DACs in each group of DACs determines a relative weighting of the weighted signals, where relative weighting determining an output phase of an output signal of the phase rotator. The DACs are configured to adjust the output phase of the phase rotator. At a kphase, N/4 adjacent DACs are activated that are indexed as m, m,. . .

US Patent:

7508272, Mar 24, 2009

Filed:

Sep 24, 2007

Appl. No.:

11/902604

Inventors:

Siavash Fallahi - Newport Coast CA, US
Chun Ying Chen - Irvine CA, US
Mark J. Chambers - Mission Viejo CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03L 7/00

US Classification:

331 2, 331 45

Abstract:

A system for generating multiple synthesized clocks having an input terminal for receiving a reference signal, a phase locked loop circuit coupled to the input signal terminal, where the phase locked loop circuit is capable of generating a plurality of output signals that are frequency locked to the reference signal and having a plurality of different phases, a phase rotator coupled to the phase locked loop circuit, where the phase rotator generates an even greater plurality of phases.

US Patent:

7656986, Feb 2, 2010

Filed:

May 23, 2008

Appl. No.:

12/153782

Inventors:

Chun Ying Chen - Irvine CA, US

Assignee:

Broadcom Corporation - Irvine CA

International Classification:

H03D 3/24
H04L 23/00

US Classification:

375375, 375354, 375371, 375372, 375373, 375374, 375376

Abstract:

A phase rotator generates an output signal having plurality of possible output phases with reduced phase jitter. The low jitter phase rotator includes a plurality of differential amplifiers configured to receive a plurality of input differential signals having different phases, and configured to generate a plurality of weighted signals responsive to the plurality of input differential signals. A plurality of digital-to-analog converters (DAC) are arranged into a plurality of groups, each group of DACs configured to provide current for one of the corresponding differential amplifiers. The number of active DACs in each group of DACs determines a relative weighting of the weighted signals, where relative weighting determining an output phase of an output signal of the phase rotator. The DACs are configured to adjust the output phase of the phase rotator. At a kphase, N/4 adjacent DACs are activated that are indexed as m, m,. . .