Chun H Chen

US Patent:

6384447, May 7, 2002

Filed:

Aug 1, 2001

Appl. No.:

09/920214

Inventors:

Andrei Mihnea - San Jose CA
Paul J. Rudeck - Boise ID
Chun Chen - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

H01L 2976

US Classification:

257314, 257315, 36518518

Abstract:

A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by applying a first voltage to the gate, a second voltage to the drain, and a third voltage to the source. During a programming operation, the channel current is approximately zero, and the first voltage is ramped at a rate proportional to the injection current.

US Patent:

6426898, Jul 30, 2002

Filed:

Mar 5, 2001

Appl. No.:

09/797682

Inventors:

Andrei Mihnea - San Jose CA
Jeffrey Kessenich - Boise ID
Chun Chen - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 700

US Classification:

3651853, 438257, 438266, 36518511, 36518529, 365218, 365233

Abstract:

A method of erasing memory cells in a flash memory device that recombines holes trapped in the tunnel oxide (after an erase operation) with electrons passing through the tunnel oxide is disclosed. The method uses an erase operation that over-erases all memory cells undergoing the erase operation. A cell healing operation is performed on the over-erased cells. The healing operation causes electrons to pass through the tunnel oxide and recombine with trapped holes. The recombination substantially reduces the trapped holes within the tunnel oxide without reducing the speed of the erase operation. Moreover, by reducing trapped holes, charge retention, overall performance and endurance of the flash memory cells are substantially increased.

US Patent:

6434045, Aug 13, 2002

Filed:

Jun 7, 2001

Appl. No.:

09/876674

Inventors:

Andrei Mihnea - San Jose CA
Paul J. Rudeck - Boise ID
Chun Chen - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 1604

US Classification:

36518518, 36518514

Abstract:

A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by applying a first voltage to the gate, a second voltage to the drain, and a third voltage to the source. During a programming operation, the channel current is approximately zero, and the first voltage is ramped at a rate proportional to the injection current.

US Patent:

6445619, Sep 3, 2002

Filed:

Aug 1, 2001

Appl. No.:

09/920364

Inventors:

Andrei Mihnea - San Jose CA
Paul J. Rudeck - Boise ID
Chun Chen - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 1604

US Classification:

36518529, 36518514

Abstract:

A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by applying a first voltage to the gate, a second voltage to the drain, and a third voltage to the source. During a programming operation the channel current is approximately zero, and the first voltage is ramped at a rate proportional to the injection current.

US Patent:

6445620, Sep 3, 2002

Filed:

Aug 1, 2001

Appl. No.:

09/920465

Inventors:

Andrei Mihnea - San Jose CA
Paul J. Rudeck - Boise ID
Chun Chen - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 1604

US Classification:

36518529, 36518518

Abstract:

A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by applying a first voltage to the gate, a second voltage to the drain, and a third voltage to the source. During a programming operation, the channel current is approximately zero, and the first voltage is ramped at a rate proportional to the injection current.

US Patent:

6449189, Sep 10, 2002

Filed:

Aug 1, 2001

Appl. No.:

09/920460

Inventors:

Andrei Mihnea - San Jose CA
Paul J. Rudeck - Boise ID
Chun Chen - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 1604

US Classification:

36518518, 36518514

Abstract:

A flash memory cell comprises a gate, a drain, a source, a floating gate, and a control gate. The flash memory cell is capable of being programmed by inducing a voltage drop of between about four volts and six volts across a deep-depletion region by applying a first voltage to the gate, a second voltage to the drain, and a third voltage to the source. During a programming operation, the channel current is approximately zero, and the first voltage is ramped at a rate proportional to the injection current.

US Patent:

6493280, Dec 10, 2002

Filed:

Oct 22, 2001

Appl. No.:

09/982682

Inventors:

Andrei Mihnea - San Jose CA
Jeffrey Kessenich - Boise ID
Chun Chen - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 700

US Classification:

365218, 36518529, 3651853, 36518528, 36518518, 36518522

Abstract:

A method of erasing memory cells in a flash memory device that recombines holes trapped in the tunnel oxide (after an erase operation) with electrons passing through the tunnel oxide is disclosed. The method uses an erase operation that over-erases all memory cells undergoing the erase operation. A cell healing operation is performed on the over-erased cells. The healing operation causes electrons to pass through the tunnel oxide and recombine with trapped holes. The recombination substantially reduces the trapped holes within the tunnel oxide without reducing the speed of the erase operation. Moreover, by reducing trapped holes, charge retention, overall performance and endurance of the flash memory cells are substantially increased.

US Patent:

6563741, May 13, 2003

Filed:

Jan 30, 2001

Appl. No.:

09/772667

Inventors:

Andrei Mihnea - San Jose CA
Chun Chen - Boise ID
Paul Rudeck - Boise ID
Andrew R. Bicksler - Boise ID

Assignee:

Micron Technology, Inc. - Boise ID

International Classification:

G11C 1604

US Classification:

36518529, 3651853

Abstract:

A non-volatile memory device includes an improved method for erasing a block of stack-gate single transistor flash memory cells. The memory performs an efficient and controllable mode of programming, referred to as block convergence. During an erase operation, one or more electrical erase pulses of fixed number, duration and voltage waveform are applied to memory cells in an addressable block of the memory device array. The erase pulse(s) fully erase all bits in the block. A block convergence operation is applied simultaneously to all cells in the block. The block convergence operation brings a threshold voltage of cells, which may have become over-erased during the erase operation, to a controlled level. A reverse-bias pulse, capable of inducing band-to-band tunnelling across one junction in the structure of the flash memory cells, is applied to a first junction. The other junction receives either a reverse bias or floating potential.